Massachusetts Institute of Technology

Mass. Institute of Technology

Glenn H Chapman

Jack I Raffel

John A Yasaitis

Terry O Herndon

Mark L Naiman

James A Burns

A method of fabricating programmable interlayer conductive links in a multilayer integrated circuit structure, comprising the steps of forming elements of either a conductive or semiconductive material as a lower layer, depositing an insulative layer on top of the lower layer elements, implanting ions into one or more link regions of the insulative layer, forming at least one upper conductor over the implanted regions and selectively applying sufficient energy to at least one of the implanted regions of the integrated circuit structure to render the selected link region conductive. The invention also embraces customized integrated circuit structures with interlayer conductive paths made in accordance with this method.

Selectively programmable interconnections in multilayer integrated

A method of producing interlayer conductive paths having substantially planar top surfaces in a multilayer integrated circuit structure, comprising the steps of forming elements of either a conductive or semiconductive material as a lower layer, depositing an insulative layer on top of the lower layer elements, implanting ions into one or more selected regions of the insulative layer, forming at least one upper conductor over the selected regions and sintering the integrated circuit structure sufficient to render the selected regions conductive. The invention also embraces an integrated circuit structures with interlayer conductive paths made in accordance with this method.

Fabrication of interlayer conductive paths in integrated circuits

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer and a second metal layer. Diffusion barrier may be employed between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

Method of forming conductive path by low power laser pulse

A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.

Method and apparatus for forming low resistance lateral links in a

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer, a second metal layer and diffusion barrier layers between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

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Bedford, MA, United States of America

Glenn H Chapman