Freescale Semiconductor,inc.

Intel Corporation

Motorola Corporation

Glenn E Starnes

Daniel Cummings

Amir Javidi

Ray Chang

Mark W Jetton

Stephen T Flannagan

Bradley J Garni

Thomas W Liston

William R Weier

Lawrence N Herr

Lawrence F Childs

Olga R Lu

Huy Van V Pham

Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

Area-efficient scalable memory read-data multiplexing and latching

A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

Bypass system and method that mimics clock to data memory read timing

A memory having at least one memory array block, the at least one memory array block comprising N wordlines, wherein N is greater than one, is provided. The memory comprises a plurality of sense amplifiers coupled to the at least one memory array block. The memory further comprises at least one dummy bitline, wherein the at least one dummy bitline comprises M dummy bitcells, wherein M is equal to N. The memory further comprises a timing circuit coupled to the at least one dummy bitline, wherein the timing circuit comprises at least one stack of pull-down transistors coupled to a sense circuit for generating a latch control output signal used for timing control of memory accesses. Timing control may include generating a sense trigger signal to enable the plurality of sense amplifiers for read operations and/or generating a local reset signal for terminating memory accesses, such as disabling the plurality of write drivers for write operations.

Memory having a dummy bitline for timing control

A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that is coupled to each of the plurality of clock driver circuits. The latch is for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. The timing control circuit removes complex logic gates from the clock critical timing paths. Also, circuit topology is simplified allowing improved critical timing performance. Also, all of the clock driver circuits share a common latch control to improve clock recovery synchronization and reduce a risk of initializing the clock timing circuit in the wrong logic state.

Self-timed memory having common timing control circuit and method therefor

A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.

Multiple block memory with complementary data path

Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.

Integrated circuit memory having a fuse detect circuit and method

A memory utilizing programmable delay circuits to control address buffers. A programmable delay device is provided for each block of a plurality of blocks of the memory device. Each block is associated with a corresponding bit array for storing data for the associated block. The delay device is used to delay activation of sense amplifiers from the time the block is selected which, in turn, corresponds to the duration of the addresses that are provided to the bit array within the block. Each of the delays within each block is programmed by a global fuse circuit, so that all of the blocks are programmed with the same delay. After fabrication of the memory device onto an integrated circuit (IC), all of the data paths within each block are measured under various voltage and temperature conditions to identify the slowest data path of all blocks of the memory device. Once a particular delay is identified for the slowest data path within the memory device, all of the programmable delays within each block are programmed with a corresponding delay. In this manner, all of the sense amplifiers within any selected blocks are activated after the programmed delay to ensure valid data. A similar delay device is provided within the clock control circuitry to pulse-width control the clock signal provided to the address buffers. The global fuse circuit used to program the delay device within each of the blocks is also used to program the delay device within the clock control circuit so that the program delay within the clock control circuit and the data blocks are essentially the same.

Memory utilizing a programmable delay to control address buffers

An integrated circuit memory (114) has a power supply independent address buffer (50) that comprises an inverter (60), a bipolar transistor (67), and a P-channel transistor (68). The inverter (60) has an output terminal coupled to a base of the bipolar transistor (67). The P-channel transistor (63) is for injecting a current at the output terminal of the inverter in response to a reference voltage. The reference voltage varies proportionally to variations of a power supply voltage in order to compensate for gate-to-source voltage changes of a P-channel transistor (61) of the inverter (60) that occurs as a result of a changing power supply voltage. For address buffer (50), a range of address transition times as a function of power supply voltage is decreased, thus improving an address set-up and hold time of the integrated circuit memory (114).

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Austin, TX, United States of America

Glenn E Starnes