Ford Microelectronics, Inc.

Other

Glenn E Noufer

David P Laude

A delay stage for use in a voltage-controlled delay chain of a delay locked loop or in a voltage-controlled ring oscillator of a phase locked loop has pullup and pulldown transistors driven by a first input to the delay stage, at least one of which is in series with a delay control transistor, and a second pullup and pulldown transistor gated by a second input to the delay stage. When used in a delay chain, the first input is driven by a signal that leads the second input to the delay stage.

High speed circuit of particular utility in delay and phase locked loops

A GaAs logic circuit including a current control FET that provides high current for switching an output FET, but limits the forward biasing of the output FET at the end of a transition to input logic 1 by controlling the steady state value of current to a gate of the output FET, which limits the voltage applied to the gate of the output FET to a given value. A bias circuit referenced to the voltage applied to the source of the output FET applies a nominal gate voltage to the current control FET. The value of the nominal gate voltage is such as is required to limit the value of the steady state current to the gate of the output FET to that which limits the voltage applied to such gate to the desired given value. Such nominal gate voltage is obtained by shifting the source voltage by the amount of the nominal threshold voltage V.sub.Te of an enhancement-mode FET of the bias circuit. If the nominal threshold voltage V.sub.Te varies from nominal in processing or due to operating temperature variations, the bias circuit shifts the gate voltage from nominal so that the actual voltage applied to the gate of the current control FET offsets the corresponding increase in the threshold voltage of the current control FET. As a result, the actual steady state current conducted by the GaAs logic circuit is relatively independent of such process and temperature variations.

FET gate current limiter circuit

A GaAs logic circuit uses a first FET to control the application of a logic signal from an input to an output. The first FET inherently has parasitic gate-to-source and gate-to-drain diodes. A control signal applied to the gate of the first FET controls the application of the logic signal to the output through the first FET. For a first FET that is an enhancement mode GaAs device, the gate current tends to forward bias such diodes under all operating conditions and tends to significantly increase the gate current. For a first FET that is a depletion-mode device, adverse operating temperatures can cause such tendency to forward bias these diodes and other circuit diodes. A limiter FET connected to the gate to limit the gate current and thus limits the forward biasing of the parasitic and circuit diodes. This reduces the effect on the gate current of variations in the power supplies to the FET, process variations and operating temperature variations. Limiting the gate current also limits the voltage drop resulting from the source resistance of the first FET, maintaining the voltage swing of the logic signal at the output at desired levels. If the gate current were not limited, the resulting greater forward bias of those diodes would cause an increase in the current drain from a voltage supply that biases the first FET. The unlimited forward bias would also result in a greater voltage drop from drain-to-source across the first FET, reducing the V.sub.OL at the output and resulting in lower noise margin.

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Chipita Park, CO, United States of America

Glenn E Noufer