Motorola Corporation

Glenn E Noufer

William J Donoghue

A circuit uses a pair of transistors in series to provide an output pulse which indicates an address transition has occurred. A duration of joint conductivity of the pair of transistors determines the duration of the output pulse. For an address transition, one of the transistors is rapidly turned on while the other is slowly turned off with a slow fall time. The fall time is adjustable to achieve an adjustable duration of joint conductivity, and thereby an adjustable output pulse width.

Circuit for address transition detection

A four-state ROM cell is improved by providing a tapered potential gate area which allows for the effective gate width to be increased and the gate length to be decreased for each succeedingly higher gain state with a single program mask at the polysilicon gate deposition stage.

Four-state ROM cell with increased differential between states

A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without static current flow when the TTL is a logic '1' by isolating the input from an input P channel transistor and using feedback from an input N channel transistor to turn off the P channel transistor. A second P channel transistor is used to couple a positive power supply voltage to the input P channel transistor in response to an output from the N channel transistor.

TTL to CMOS input buffer

A CMOS level shifter with a reference voltage generator provides a TTL to CMOS input buffer. The reference voltage generator provides a reference voltage which is responsive to the voltage level of the TTL input signal. The reference voltage is kept sufficiently low to prevent an input P channel transistor from turning on when the TTL input signal is at a logic high even when the voltage level is at a minimum for a logic high.

TTL To CMOS input buffer

A TTL to CMOS input buffer accomplishes buffering a TTL signal to a CMOS signal without requiring current flow through a CMOS input inverter in a static condition by introducing a reference voltage to match the lowest level of a logic '1' of the TTL signal. The input inverter has a P channel transistor which, by having a source at the reference voltage, does not turn on when the TTL signal is at the lowest level of a logic '1'. The reference voltage is selected to be less than the lowest level of a logic '1' minus the threshold voltage of the P channel transistor.

TTL to CMOS Input buffer

A reference voltage generator uses a resistor divider technique to develop a reference voltage, but a resistor is replaced by a transistor to provide improved compensation for changes in a power supply voltage. The transistor is coupled to provide resistance which varies inversely to variations in power supply voltage.

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Austin, TX, United States of America

Glenn E Noufer