International Business Machines Corporation

Glenn E Holmes

Timothy Gerard McNamara

Kevin Charles Gower

Patrick James Meaney

Frank David Ferraiolo

Natesan Venkateswaran

Paul David Muench

Steven Magdo

Jonathan Yang Chen

Nagashyamala R Dhanwada

William J Scarpero, Jr

Raymond J Ferreri

Joseph K Morrell

Jose Luis P Correia Neves

An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.

Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface

An abstraction based multi-phase method for VLSI chip floorplanning is described. The abstraction based approach provides a solution to macro floorplanning in the presence of leaf level intermediate logic, and achieves it without loss of accuracy in the results. Annotations generated during abstraction are presented as floorplanning constraints which account for the abstracted data. The floorplanning and placement algorithms handle detailed netlists consisting of large blocks and small leaf level cells in an efficient manner. The abstraction based approach phases out by abstracting the leaf level logic (thus reducing the solution space of the floorplanner) and reintroducing them in the form of floorplan constraints (to account for the presence of the leaf level logic while determining the location of large blocks). The abstraction and bundling phases achieves a significant improvement in the performance of a simulated annealing based floorplanner. The overall concept of driving a floorplanning algorithm with a path based hyper-edge representation also helps to provide structural information about the netlist to the floorplanner.

Method for optimizing a VLSI floor planner using a path based hyper-edge representation

An exemplary embodiment of the invention is a method and apparatus for configuring system cycle time in a data processing system with at least one master latch clock generating a master latch clock signal and at least one slave latch clock generating a slave latch clock signal. Timing errors are detected during system hardware testing. Adjustments to the system timing are calculated based on error for at least one of a master latch clock signal and a slave latch clock signal. The on-cycle edge of at least one of the master latch clock signal and slave latch clock signal is adjusted based on the calculations while maintaining a corresponding mid-cycle edge of at least one of the master latch clock signal and the slave latch clock signal.

System and method for adjusting timing parts

A lock circuit for indicating a locked/unlocked condition of phased lock loops circuits, which uses a reference clock signal input to a good-cycle counter and to a bad-cycle counter to signal a set/reset latch to output a signal indicating whether or not the phase of the output signal and input clock are in phase. Phase detector inputs are XOR gated to produce a pulse when the phase locked output clock is in a bad cycle indicated by the phase locked output clock not being in-phase with its input clock. Pulses on the XOR gate output on a bad cycle feed a single cycle counter reset circuit. The single cycle counter reset circuit on every cycle resets one of the bad and good counters based on its detection of a bad cycle pulse from the XOR gate. The good-cycle counter's output is to the SET input of the set/reset latch, and the bad-cycle counter's output is to the RESET input of the set/reset latch . We enable specific cycling of both the good and bad counters.

Lock/unlock indicator for PLL circuits

An automated, custom personalization process for generating integrated gate array chips is defined which enhances yield and reliability potential. Unused data provided in the general purpose design is deleted through a selective detection procedure based on circuit utilization.

Method of integrated circuit chips design

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Wappingers Falls, NY, United States of America

Glenn E Holmes