Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Other

Air Products and Chemicals, Inc.

Agere Systems Optoelectronics Guardian Corp.

Glenn B Alers

Pradip Kumar Roy

Sailesh Mansinh Merchant

Robert Bruce Van Dover

Gordon Albert Thomas

Bonnie E Weir

Robert McLemore Fleming

Kathleen Susan Krisch

David A Roberts

John Anthony Thomas Norman

Arthur Kenneth Hochberg

Seungmoo Choi

Ruichen Liu

Barry Franklin Levine

Daniel Joseph Vitkavage

Anthony Thomas Fiory

Tseng-Chung Lee

Don X Sun

Yoshihide Senzaki

Philip W Diodato

Helen Louise Maynard

Timothy J Klemmer

Kenneth Alexander Ellis

Robert J Chichester

Pradip Kimar Roy

A method is disclosed for processing a silicon workpiece including a hybrid thermometer system for measuring and controlling the processing temperature where fabrication materials have been or are being applied to the workpiece. The hybrid thermometer system uses optical reflectance and another thermometer technique, such as a thermocouple and/or a pyrometer. Real-time spectral data are compared to values in a spectrum library to determine the &ldquo;surface conditions&rdquo;. A decision is then made based on the surface conditions as to how the temperature is measured, e.g., with optical reflectance, a pyrometer, or a thermocouple, and the temperature is measured using the appropriately selected technique. Utilizing the hybrid thermometer system, the temperature of a silicon workpiece may be accurately measured at low temperatures while accounting for the presence of fabrication materials.

Method for processing silicon workpieces using hybrid optical thermometer system

A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on the top surface of the dielectric layer. A second layer of conductor is disposed on top of the dielectric material layer, thus completing the capacitor structure.

Damascene capacitors for integrated circuits

A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer. The metal for the top plate of the capacitor is then deposited over the interconnect layer. The top plate of the capacitor extends into the trench. The metal layer and barrier layer are then patterned to form the top plate of the capacitor.

Process for fabricating an integrated circuit device having capacitors with a multilevel metallization

Complex mixed metal containing thin films can be deposited by CVD from liquid mixtures of metal complexes without solvent by direct liquid injection and by other precursor dispersing method such as aerosol delivery with subsequent annealing to improve electrical properties of the deposited films. This process has potential for commercial success in microelectronics device fabrication of dielectrics, ferroelectrics, barrier metals/electrodes, superconductors, catalysts, and protective coatings. Application of this process, particularly the CVD of ZrSnTiOx (zirconium tin titanate, or ZTT) and HfSnTiOx (hafnium tin titanate, or HTT) thin films has been studied successfully.

Deposition and annealing of multicomponent ZrSnTi and HfSnTi oxide thin films using solventless liquid mixture of precursors

The present invention provides a semiconductor device that has a metal barrier layer for a dielectric material, which can be used in an integrated circuit, if so desired. The semiconductor device provides a capacitance to the integrated circuit and in a preferred embodiment comprises a first layer located on a surface of the integrated circuit. A metal barrier layer is located on the first layer and is susceptible to oxidation by oxygen. A high K capacitor dielectric layer (i.e., a higher K than silicon dioxide) that contains oxygen, such as tantalum pentoxide, is located over the metal barrier layer. The semiconductor device further includes a first layer located over the high K capacitor dielectric layer.

Semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and a method of manufacture thereof

An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.

Integrated circuit device having dual damascene capacitor

In accordance with the invention, magnetostrictive saw devices are provided with improved transducer structures for enhanced performance. In one improved device, the transducers are in the form of gratings with interconnected ends for reduced resistance and inductance. In another embodiment, the transducers are shaped to provide apodization. In yet a third embodiment, transducer performance is enhanced by patterning composite structures.

Magnetostrictive surface acoustic wave devices having optimized transducers

A method of forming a capacitor having a tungsten bottom electrode in a semiconductor wafer that eliminates the effects of oxidation of the surface of the bottom electrode on capacitor performance.

Method of forming a capacitor having a tungsten bottom electrode in a semiconductor wafer

An electronic device having an improved capacitor structure is formed by depositing a metal layer defining a first electrode on a film of high dielectric constant material, and then depositing the dielectric layer of the capacitor structure on the first electrode. This resulting structure is then exposed to a nitrogen plasma and the top electrode is formed. Exposing the first electrode to a plasma of pure nitrogen prevents the partial oxidation of the first electrode and reduces the density of charge traps at the electrode/dielectric interface. The dielectric film is passivated with the nitrogen material before forming the top electrode to prevent interdiffusion between the electrode and the dielectric.

Method for making field effect devices and capacitors with thin film dielectrics and resulting devices

The present invention relates to a conductive plug capacitor and method of making for use in multi-level integrated circuit structures. In one embodiment, a tungsten plug is formed in a window in a dielectric layer and thereafter a cavity is formed in the plug. This cavity in the plug may serve as the lower electrode for the capacitor, with a layer of dielectric deposited in the cavity and a top metal electrode deposited on the dielectric layer. An alternative embodiment makes use of not only the inner cavity surfaces of the cavity in the tungsten plug, but also the outer sidewalls of the tungsten plug. To this end, after formation of the tungsten plug heading the cavity formed therein, a partial etchback of the dielectric layer in which the tungsten plug is formed is effective. The capacitor dielectric is then deposited on the sidewalls, the top surface and the interior of the cavity of the tungsten plug thereby increasing the area and thereby the over capacitance.

A method for making an integrated circuit capacitor which in one embodiment preferably comprises the steps of: forming, adjacent a semiconductor substrate, a first metal electrode comprising a metal nitride surface portion; forming a tantalum pentoxide layer on the metal nitride surface portion while maintaining a temperature below an oxidizing temperature of the metal; remote plasma annealing the tantalum pentoxide layer; and forming a second electrode adjacent the tantalum pentoxide layer. The step of forming the tantalum pentoxide layer preferably comprises chemical vapor deposition of the tantalum pentoxide at a temperature below about 500&deg; C. Accordingly, oxidation of the metal is avoided and a high quality tantalum pentoxide is produced. The metal of the first metal electrode may comprise at least one of titanium, tungsten, tantalum, and alloys thereof.

Method for making an integrated circuit capacitor including tantalum pentoxide

An improved surface acoustic wave device includes a film of a magnetostrictive material disposed on a substrate and spaced apart input and output transducer elements disposed on the film. The input element causes horizontally polarized shear waves to propagate along the film via the magnetostriction of the film. The shear waves propagating along the film are received by the output transducer element. The SAW device can be integrated on a microelectronic circuit useable in single chip radio frequency applications.

Magnetostrictive surface acoustic wave device and microelectronic

The breakdown of an ultra-thin dielectric layer is detected by applying a test signal to the layer. Measurements are taken of noise signals present in the layer during the application of the test signal. At breakdown, a significant increase occurs in the amplitude of the measured noise signals. Similarly, fluctuations in quiescent current, I.sub.DDQ, (I.sub.DDQ noise signals), rather than the values of I.sub.DDQ, are utilized during testing as the basis for detecting defects in integrated circuits.

Detecting defects in integrated circuits

Apparatus for processing a silicon workpiece uses reflected UV light to measure and control the workpiece temperature. A linearly polarized beam including UV light is directed onto a silicon surface to produce a reflected beam. The reflected beam is cross-polarized to null out much of the light, and the resulting residual reflectivity spectrum is determined. The temperature is determined from the characteristics of this spectrum. A workpiece heating station uses this measuring technique to accurately control the temperature of a silicon workpiece and temperature-dependent processing over a wide range of processing temperatures, including temperatures below 500.degree. C.

Apparatus for processing silicon devices with improved temperature

An electronic device is formed by depositing a thin film of high dielectric constant material on a silicon substrate, exposing the structure to plasma, and then forming the top electrode. The plasma substantially reduces the density of charge traps at the dielectric/silicon interface. Advantageously, the dielectric film is passivated with a nitrogen-containing material before forming the top electrode to prevent interdiffusion between the electrode and the dielectric.

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Santa Cruz, CA, United States of America

Glenn B Alers