Infineon Technologies Ag

Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Hitachi, Ltd.

Glenn Ashley Farrall

Frank Hellwig

Albrecht Mayer

Neil Stuart Hastie

Simon Brewerton

Antonio Vilela

Sandeep Vangipuram

Gerhard Wirrer

David Alan Edwards

Klaus Oberlaender

Andrew Craig Sturges

Catherine Louise Barnaby

Darren Galpin

Richard Knight

Boyko Traykov

Paul Hubbert

Bruno Fel

Michael Goessel

Andrew Michael Jones

Thomas Rabenalt

Anthony Willis Rich

Ketan Dewan

Sivaram Krishnan

Simon Cottam

Atsushi Hasegawa

Chih-Jui Peng

David Addison

Dietmar Koenig

Margaret Rose Gearty

David May

Robert Wiesner

Rainer Faller

Joerg Syassen

Manfred Zimmerman

Trevor Bird

Shubhendu Mahajan

Alfred Eder

Andrew Keith Betts

Brian Foster

A non-volatile memory (NVM) system external to a processor comprising an NVM and a memory controller may perform various aspects of the techniques. The NVM may store a first cryptographic signature and first data. The memory controller may, responsive to a first write request to write updated data to at least a portion of the NVM, to store the updated data in the NVM along with the first data to create second data. The memory controller may also generate, a second cryptographic signature that always differs from the first cryptographic signature, and store the second cryptographic signature as a current cryptographic signature. The memory controller may further output, to the processor, the current cryptographic signature as a reference signature, where the memory controller always replaces the current cryptographic signature, with cryptographic properties, whenever the NVM is written to and does not otherwise permit writing the current cryptographic signature.

Secure storage architectures for computing devices

A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

Systems, devices, and methods for dynamic allocation

An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.

Interconnection of protected information between components

A non-volatile memory (NVM) integrated circuit device includes a processing device and an NVM array of memory cells partitioned into a first physical region and a second physical region. The NVM integrated circuit device also includes a plurality of routing circuits, a first decoder associated with a first routing circuit, and a second decoder associated with a second routing circuit. The NVM integrated circuit device also includes a first programmable register coupled to the plurality of routing circuits, wherein the first programmable register is to store a first multi-bit value, the first multi-bit value programmed by the processing device to configure a first address range associated with the first decoder. The NVM integrated circuit device also includes a second programmable register coupled to the plurality of routing circuits, wherein the second programmable register is to store a second multi-bit value, the second multi-bit value programmed by the processing device to configure a second address range associated with the second decoder.

Flexible support for device emulation and bank swapping

Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

Write busy signaling for interface structures

A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.

Control system for process data and method for controlling process data

A System on Chip (SoC), including a plurality of processor cores including a secure master, which is configured to run security software, and a non-secure master, which is configured to run non-security software; a resource configured to be shared by the secure master and the non-secure master; and a state machine configured to protect the resource by allowing only the secure master to transition the resource to a particular state of the state machine, and allowing only the non-secure master to transition the resource to another particular state of the state machine.

Resource protection

A service request interrupt router having an interrupt controller mapped to an Interrupt Service Provider (ISP) having virtual ISPs; Service Request Nodes (SRNs) configured to convert respective interrupt signals to corresponding service requests, wherein each of the SRNs is configured to direct its service request to one of the virtual ISPs; and an arbitrator configured to arbitrate among the virtual ISPs in a time-sliced manner, and for each of the virtual ISPs, to arbitrate which of the service requests directed thereto has a highest priority.

Service request interrupt router for virtual interrupt service providers

A method includes associating an associated processor address register with a predetermined operation, invoking an instruction including a reference to a referenced processor address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.

Control system and method of memory access

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Safety hypervisor function

A memory protector is configured to evaluate access requests referring to a memory address space. The access requests comprise address parameters referring to addresses of the memory address space. The memory protector comprises an address evaluator, an address results combiner, and a data register. The address evaluator is configured to evaluate whether the address parameters refer to address ranges of a set of address ranges and is configured to provide results regarding the address ranges. The address results combiner is configured to combine results provided by the address evaluator depending on access protection groups to which the address ranges are mapped to. The memory protector is configured to provide access grant results based on combinations provided by the address results combiner. The data register is configured to store data concerning the set of address ranges and concerning a mapping of the address ranges to the access protection groups.

Memory protecting unit and method for protecting a memory address space

An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

Virtual machine monitor interrupt support for computer processing unit (CPU)

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

System and method for signature-based redundancy comparison

Growing community of inventors

Long Ashton, United Kingdom

Glenn Ashley Farrall