Advanced Micro Devices Corporation

Glenn A Tamura

Prem Sobel

Brian D McMinn

Thomas W Lynch

Robert C Thaden

Robert M Perlman

Raju Vesgesna

An arithmetic logic unit includes structure for calculating in at least two stages, this structure including substructure for calculating in each of the at least two stages at least partially at the same time and substructure for ensuring the substructure for calculating in each of the at least two stages performs only one calculation at a time. Accumulators that work with pipe stages of a floating point unit may form all of part of the calculating structure. A method of performing calculations includes the steps of separating the calculations into at least two stages and separately accumulating the results of the stages using at least two accumulators, one each accumulator for each calculation at each of the at least two stages.

Arithmetic unit having multiple accumulators

A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.

Pipelined floating point processing unit

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Austin, TX, United States of America

Glenn A Tamura