Intel Corporation

Daedalus Prime LLC

Tahoe Research, Ltd.

Glenn A Glass

Anand S Murthy

Tahir Ghani

Jack T Kavalieros

Chandra S Mohapatra

Karthik Jambunathan

Harold W Kennel

Willy Rachmady

Seung Hoon Sung

Gilbert W Dewey

Stephen M Cea

Matthew V Metz

Benjamin Chu-Kung

Daniel Bourne Aubertine

Kelin J Kuhn

Siddharth Chouksey

Seiyon Kim

Roza Kotlyar

Biswajeet Guha

Ashish Agrawal

Van H Le

Annalisa Cappellani

Cory C Bomberger

Nabil G Mistkawi

Michael J Jackson

Boyan Boyanov

Michael L Hattendorf

Sean T Ma

Susmita Ghose

Subhash M Joshi

Dipanjan Basu

Saurabh Morarka

Ying Pang

Marko Radosavljevic

Patrick R Morrow

Prashant Majhi

Mauro J Kobrinsky

Jun Sung Kang

Andrew N Westmeyer

Thomas Hoffmann

Gaurav Thareja

Ravi Pillarisetty

Han Wui Then

Niloy Mukherjee

Rafael Rios

Rishabh Mehandru

Mark Y Liu

Dax M Crum

Zachary Geiger

Jitendra Kumar Jha

Thomas Hoffman

Jeffrey R Wank

Ju H Nam

Mark R Brazier

Sansaptak W Dasgupta

Walid M Hafez

Paul B Fischer

Cory E Weber

Szuya S Liao

Peter G Tolchinsky

Patrick H Keys

Ryan Keech

Srijit Mukherjee

Dan S Lavric

Suresh Vishwanath

Aravind S Killampalli

Chris Auth

Hei Kam

Koustav Ganguly

Rushabh Shah

Thomas T Troeger

Nayanee Gupta

Jaya P Gupta

Cheng-Ying Huang

Leonard P Guler

Nicole K Thomas

Huang-Lin Chao

Sanaz Kabehie Gardner

Rahul Ramaswamy

Ehren Mannebach

Nick Lindert

Nidhi Nidhi

Nazila Haratipour

Nadia M Rahhal-Orabi

Bruce E Beattie

Anupama Bowonder

Gopinath Bhimarasetti

Justin R Weber

Arnab Sen Gupta

Johann Christian Rode

Ritesh Jhaveri

Chytra Pawashe

Daniel Pantuso

Jacob M Jensen

Owen Y Loh

Heidi M Meyer

Mengcheng Lu

Subrina Rafique

Robert Ehlert

Ted E Cook, Jr

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology

An integrated circuit structure includes a first non-planar semiconductor device and a second non-planar semiconductor device. The first non-planar semiconductor device includes a first body, a first gate structure at least in part wrapped around the first body, and a first source region and a first drain region. The first body extends laterally between the first source and first drain regions. The second non-planar semiconductor device comprises a second body, a second gate structure at least in part wrapped around the second body, and a second source region and a second drain region. The second body extends laterally between the second source and second drain regions. In an example, a first height of the first body is at least 5% different from a second height of the second body. Each of the first and second bodies can be, for instance, a nanoribbon, nanosheet, or nanowire.

Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation

Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi.

Integrated circuit structures including a titanium silicide material

Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

Contact resistance reduction in transistor devices with metallization on both sides

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure is in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Integrated circuit structures having germanium-based channels

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling ('BTBT') effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

Reducing off-state leakage in semiconductor devices

Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.

Gate-all-around integrated circuit structures having germanium-doped nanoribbon channel structures

Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

Low resistance approaches for fabricating contacts and the resulting structures

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Self-aligned 3-D epitaxial structures for MOS device fabrication

Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.

Techniques for achieving multiple transistor fin dimensions on a single die

Growing community of inventors

Portland, OR, United States of America

Glenn A Glass