Xilinx, Inc.

Glenn A Baxter

Kiran B Buch

Edwin S Law

Raymond C Pang

Khang Kim Dao

Andy H Gan

Christopher J Borrelli

Jennifer R Lilley

Paul M Hartke

Brian L Forsse

A processor module can include a circuit board, a first programmable circuitry coupled to the circuit board, wherein the first programmable circuitry is configurable to implement different physical circuits, and a processor configured to execute program code. The processor can be coupled to the circuit board and to the first programmable circuitry. The processor module also can include random access memory (RAM) devices coupled to the circuit board and electrically coupled to the first programmable circuitry. The RAM devices can be coupled to the first programmable circuitry to form parallel channels of the RAM devices. The processor module further can include an interface coupled to the circuit board and electrically coupled to the first programmable circuitry for coupling input and output between the first programmable circuitry and external circuitry.

Computing system with network attached processors

A graphical user interface (GUI) used to program complex hardware elements is provided that allows a variety of files to be used to control subsequent content displayed by the GUI. The control includes dynamic updating of actual GUI elements, as well as rule checking based upon data entered into the GUI. Configuration, rule, and GUI files can be used to control the eventual programming of the complex hardware elements. Graphical metaphors are established to enable the viewing of performance information and using that information to control the programming of the complex hardware elements.

Graphical user interface (GUI) including input files with information that determines representation of subsequent content displayed by the GUI

A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to external circuitry, and a plurality of memory modules, each memory module disposed within one of the sockets. The memory module includes a circuit board, an integrated circuit device having configurable blocks, DRAM devices that form parallel channels of DRAM memory and flash memory devices that form parallel channels of flash memory. The memory module also includes an interface electrically coupled to the integrated circuit device for coupling input and output between the integrated circuit device and external circuitry.

Data storage system with removable memory module having parallel channels of DRAM memory and flash memory

Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

Port interface modules (PIMs) in a multi-port memory controller (MPMC)

Access is provided to user registers of a user design implemented on an integrated circuit (IC). A memory of the IC is initialized with instructions, and a portion of the programmable logic and interconnect resources of the IC is configured to implement an access interface, multiplexer logic, and the user design. A processor is coupled to the programmable logic and interconnect resources and executes the instructions from the memory. The processor receives from an external user interface, via the access interface, an access command. For a read command, the processor reads a value from an identified user register and transmits the value to the external user interface. For a write command, the processor writes a write value specified by the access command to the specified user register via the multiplexer logic. The processor and the user design are both coupled to write to the user registers via the multiplexer logic.

Accessing user registers in an integrated circuit

Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow.

Performance monitors (PMs) for measuring performance in a system and providing a record of transactions performed

A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.

Self aligning state machine

Various embodiments of the invention provide a method for transferring communication data through one or more pins of a programmable logic device (PLD). The PLD includes a configuration port that may be used to program programmable logic and interconnect resources of the PLD. The programmable logic and interconnect resources include the input/output blocks of the PLD. Portions of the communication data are sequentially transferring between certain pins of the PLD and certain input/output registers in one or more input/output blocks associated with the pins. A frame of configuration data including a portion of the communication data is transferred between the input/output registers and a frame register of the configuration port of the PLD. Formats are converted between the portion of the communication data and the frame of the configuration data in the frame register of the PLD.

Data transfer using the configuration port of a programmable logic device

Method and apparatus for communicating data between a network transceiver and memory circuitry is described. In one example, a transmit peripheral includes a streaming interface configured to receive a communication sequence having data read from the memory circuitry. A receive peripheral includes a streaming interface configured to transmit a communication sequence having data to be written to the memory circuitry. Media access control (MAC) circuitry is configured to transmit the data read from the memory circuitry to the network transceiver, and receive the data to be written to the memory circuitry from the network transceiver.

Method and apparatus for communicating data between a network transceiver and memory circuitry

A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user's needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD. Finally, the functions of the processor local bus can be efficiently limited, thereby allowing the PLD to approach the performance level of an ASIC.

Programmable logic device including programmable interface core and central processing unit

Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing system. A plurality of ports is respectively coupled to said plurality of bus interfaces. Arbitration logic is configured for communication with the plurality of ports. The arbitration logic arbitrates access to the memory circuitry among the plurality of bus interfaces on a time shared basis.

Method and apparatus for controlling access to memory circuitry

Method and apparatus for controlling direct access to memory circuitry by a device is described. In one example, a streaming interface is configured to transmit and receive a communication sequence to and from the device. Control logic is configured to implement a plurality of direct memory access (DMA) engines. The DMA engines are configured to read and write data to and from the memory circuitry. A set of registers is configured to store control data for the plurality of DMA engines.

Method and apparatus for controlling direct access to memory circuitry

Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

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Los Gatos, CA, United States of America

Glenn A Baxter