Unisys Corporation

Glenn A Arbanas

Bruce H Williams

Roy E Greeff

Christopher R Keate

Valjean P Snyder

Rov E Greeff

Jeffery M Thornock

Bruce Howard Williams

A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.

Digital/analog bit synchronizer

An improved quadrature phase shift key modulator circuit of the type which includes a non-linear amplifier in the transmitter and includes a frequency select logic circuit for receiving the in phase and quadrature phase digital data to be modulated onto a carrier frequency signal. The output of the frequency select circuit produces select signals that are coupled to the input of a digital carrier frequency generator. The digital carrier frequency generator synthesizes and increases, decreases, or leaves unchanged the carrier frequency as a representation of the data occurring on the in phase and quadrature phase input lines. The output of the digital carrier frequency generator is smoothed and converted to an analog signal which has a constant vector power magnitude during phase change. The constant vector power when amplified in a non-linear amplifier of the transmitter is not susceptible to regeneration of side lobes of the carrier signal, thus, provides a more narrow bandwidth modulated carrier frequency signal.

Offset quadrature phase shift keyed modulation circuit

An improved phase locked indication circuit for a Costas QPSK carrier recovery loop comprises an inphase channel, a quadrature channel and phase error channel each connected to an input of a three input summing circuit through a diode square law multiplier and wherein the error channel signal is filtered by a low pass filter to smooth the signal before being applied to the negative input of the summing circuit to diminish false lock and not locked signals. The locked and not lock conditions are separated one from the other by a large signal to noise ratio.

Phase lock indicator circuit for a high frequency recovery loop

An improved digital data modulator is provided for a digital transmitter. The digital data modulator comprises of a pair of digital data synthesizers which are controlled in a manner which produces complex conjugate modulated data signals of the input signals. Summing means are provided to sum the outputs of the digital data synthesizers in a manner which removes the imaginary components and simultaneously reduces the side load power without employing conventional filters.

BPSK modulator for a digital signal transmitter

A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Digitally implemented phase and lock indicators for a bit synchronizer

A novel high-speed bit synchronizer circuit comprises a phase detector having two phase detecting loops, each adapted to generate a partial error voltage signal which is summed together to provide a single phase voltage error signal which is employed to control a VCO in the return branch of both phase detecting loops. Each phase detecting loop comprises a comparator coupled to the input data stream and to a reference voltage to provide two outputs. An electronic switch is coupled to the output of each comparator and each switch has its partial error voltage output coupled through a summing circuit to the VCO, thus completing two phase detecting loops each adapted to generate a partial phase error signal indicative of the phase error between the input data stream and the recovered clock output of the VCO.

High-speed bit synchronizer

Self-clocking system for demodulating phase encoded data automatically tracks incoming data rate changes by using information from a bit synchronizer to track the incoming base band data signal.

Self-clocking system

The present invention provides a high frequency lock detecting circuit for generating a signal indicative of a locked or a not locked phase tracking condition in a phase locked loop circuit. The lock detector comprises a plurality of high speed function generators two of which are coupled to the modulated data streams for indicating the phase data streams and a third high speed function generator is coupled to the voltage error signal of the phase locked loop for indicating the absence or presence of a voltage error signal. The analog outputs of the function generators are summed together in a summing circuit and applied to a differential amplifier which removes the complex modulated data products from the output of the function generators and provides a signal which is equal to the absolute value of the data signals applied to the first function generators minus the absolute value of the error signal applied by the third function generator. The lock detection signal is applied to the sweep controls of the phase locked loop for controlling the sweep circuits associated with the voltage controlled oscillator.

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Salt Lake City, UT, United States of America

Glenn A Arbanas