Advanced Micro Devices Corporation

Legerity, Inc.

Glen W Brown

Alfredo R Linz

Martin P Soques

Carlin D Cabler

Dale E Gulick

Larry David Hewitt

David N Suggs

David E Norris

Michael Hogan

Paul G Schnizlein

Geoffrey E Brehmer

Michael E Spak

Jeffrey M Blumenthal

Ryan E Feemster

David J Guercio

Alan T Torok

Terry Lynn Cole

A communications system includes a plurality of lines, a modulator/demodulator, a processing unit, and a negotiation unit. The modulator/demodulator is coupled to the lines and adapted to communicate data over the lines using a plurality of tone sets. Each tone set is associated with a particular line. The processing unit has an amount of available processing resources for supporting the modulator/demodulator and is adapted to generate resource availability data based on the amount of available processing resources. The negotiation unit is adapted to receive the resource availability data from the processing unit and determine a subset of available tones within each tone set based on the resource availability data. The modulator/demodulator is adapted to communicate data on each line using the subset of available tones. A method for allocating the resources of a communications system includes determining an amount of available processing resources for a processing unit. The processing unit is adapted to support a plurality of connections over a plurality of lines. Each connection has an associated tone set for communicating data. A first connection is established over a first line. A first portion of the available processing resources is allocated to the first connection. A first tone range is determined based on the first portion. The first tone range is a subset of the tone set associated with the first line.

Method and apparatus for scaling modem transfer capacity in a multi-channel communications system

The present invention is for an implementation of a digital decimation filter and/or digital interpolation filter and a method of decimating and/or interpolating a multi-bit input signal, where n/2 additions are performed, where n&equals;the number of bits in each filter coefficient. Scaling and multiplication of data with coefficients is performed using a common DSP architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

Method of coding a number for storing in a memory

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

A method and apparatus is provided for regulating transmission power of a signal on a line. The method includes determining characteristics of the line, determining the transmission power needed to transmit the signal in response to the characteristics of the line, and transmitting the signal on the line in response to determining the transmission power.

Method and apparatus for power regulation of digital data transmission

The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Programmable data flow processor for performing data transfers

A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Configuring a communications system with a configurable data transfer

Communications system with a configurable data transfer architecture

The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a microcontroller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Communications system with multiple, simultaneous accesses to a memory

This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data device, such as a digital signal processor. A serial data path between the synthesizer module and the CODEC module is also included.

Audio processing chip with external serial port

The present invention is for an implementation of a multi-stage digital decimation filter and a method of decimating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. A compensation stage is also provided. Scaling and multiplication of data with coefficients is performed using a common architecture to the Decim. 2 and Decim. 3 stages. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

Implementation of a digital decimation filter and method

The present invention is for an implementation of a digital decimation filter and/or digital interpolation filter and a method of decimating and/or interpolating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. Scaling and multiplication of data with coefficients is performed using a common DSP architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

DSP architecture for a FIR-type filter and method

The present invention is for an implementation of a multi-stage digital interpolator and a method of interpolation, where n/2 additions are performed, where n=the number of bits in each filter coefficient being multiplied. Scaling and multiplication of data with coefficients is performed using a common architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

Implementation of a digital interpolation filter and method

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Monolithic PC audio circuit with enhanced digital wavetable audio

A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.

Stereo audio CODEC

This invention is for a multi-stage digital decimation filter, which includes a sinc.sup.6 filter, a half-band linear phase FIR filter and a symmetric, linear phase, FIR filter and a digital compensation filter. The multi-stage decimation filter down-samples the output of a sigma-delta modulator by a factor of about 64. The compensation filter provides compensation for rolloff introduced by the multi-stage decimation filter.

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Austin, TX, United States of America

Glen W Brown