Ramtron International Corporation

US Government as Represented by the Secretary of the Army

Fujitsu Corporation

Texas Instruments Corporation

Other

Glen Richard Fox

Ronald G Polcawich

Fan Chu

Brian Lee Eastep

Jeffrey Spencer Pulskamp

Richard Allen Bailey

Jarrod Eliason

Yoshimasa Horii

Thomas A Evans

Daniel M Potrepka

Shan Sun

Katsuyoshi Matsuura

Ko Nakamura

Tomohiro Takamatsu

Thomas E Davenport

Luz M Sanchez

Mari Tani

KouKou Suu

A ferroelectric mechanical memory structure comprising a substrate, a MEMS switch element movable between a first position and at least one second position, the MEMS switch element comprising first and second electrodes, a layer of ferroelectric material positioned between the first and second electrodes so that upon application of voltage between the first and second electrodes the MEMS switch element moves between the first position and the second position, and a switch contact which contacts the first electrode only when the MEMS switch element is in the first position, wherein the ferroelectric material is selected so that the remanent strain within the layer of ferroelectric material is controlled by the history of the voltage potential applied to the ferroelectric material by the first and second electrodes, and wherein the remanent strain is sufficient to retain the MEMS switch element in the first or second position upon removal of the voltage.

Ferroelectric mechanical memory based on remanent displacement and method

A method of making a memory device comprising a base; a capacitor comprising a ferroelectric layer and at least two electrically conductive layers, the ferroelectric layer being located between the at least two electrically conductive layers; each of the at least two conductive layers being operatively connected to a current source; a cantilever attached to the base at first end and movable at a second end, the ferroelectric capacitor being mounted to the cantilever such that the second end of the cantilever moves a predetermined displacement upon application of a current to the ferroelectric layer which induces deformation of the ferroelectric layer thereby causing displacement of the cantilever which is operatively associated with a contact so that an electrical connection is enabled with the contact upon the predetermined displacement of the cantilever. The presence or absence of a connection forms two states of a memory cell.

Ferroelectric mechanical memory and method

A ferroelectric device comprising a substrate; a textured layer; a first electrode comprising a thin layer of metallic material having a crystal lattice structure divided into granular regions; a seed layer; the seed layer being epitaxially deposited so as to form a column-like structure on top of the granular regions of the first electrode; at least one ferroelectric material layer exhibiting spontaneous polarization epitaxially deposited on the seed layer; the ferroelectric material layer, the seed layer, and first electrode each having granular regions in which column-like structures produce a high degree of polarization normal to the growth plane and a method of making.

Stylo-epitaxial piezoelectric and ferroelectric devices and method of manufacturing

A memory device comprising a base; a capacitor comprising a ferroelectric layer and at least two electrically conductive layers, the ferroelectric layer being located between the at least two electrically conductive layers; each of the at least two conductive layers being operatively connected to a current source; a cantilever attached to the base at first end and movable at a second end, the ferroelectric capacitor being mounted to the cantilever such that the second end of the cantilever moves a predetermined displacement upon application of a current to the ferroelectric layer which induces deformation of the ferroelectric layer thereby causing displacement of the cantilever which is operatively associated with a contact so that an electrical connection is enabled with the contact upon the predetermined displacement of the cantilever. The presence or absence of a connection forms two states of a memory cell.

A method for forming an electrical device having a {100}-textured platinum electrode comprising: depositing a textured metal thin film onto a substrate; thermally oxidizing the metal thin film by annealing to convert it to a rocksalt structure oxide with a {100}-texture; depositing a platinum film layer; depositing a ferroelectric film. An electrical device comprising a substrate; a textured layer formed on the substrate comprising metal oxide having a rocksalt structure; a first electrode film layer having a crystallographic texture acting as a template; and at least one ferroelectric material layer exhibiting spontaneous polarization epitaxially deposited on the first electrode film layer whereby the rocksalt structure of the textured layer facilitates the growth of the first electrode film layer with a {100} orientation which forms a template for the epitaxial deposition of the ferroelectric layer such that the ferroelectric layer is formed with an {001} orientation.

Thermally oxidized seed layers for the production of {001} textured electrodes and PZT devices and method of making

Ferroelectric memory cells () are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell () is not being accessed while avoiding significant disruption of memory cell access operations. Methods () are provided for fabricating ferroelectric memory cells () and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material () or in an encapsulation layer () formed over the patterned capacitor structure (C).

Ferroelectric capacitor with parallel resistance for ferroelectric memory

A method of fabricating a semiconductor device having a ferroelectric capacitor includes the steps of forming a lower electrode layer of the ferroelectric capacitor on an insulation film covering an active device element, forming a ferroelectric film on the lower electrode layer as a capacitor insulation film, crystallizing the ferroelectric film by applying a thermal annealing process in an atmosphere containing a non-oxidizing gas and an oxidizing gas, and forming an upper electrode layer on the ferroelectric film.

Semiconductor device having a ferroelectric capacitor and a fabrication process thereof

A method for fabrication of ferroelectric capacitor elements of an integrated circuit includes steps of deposition of an electrically conductive bottom electrode layer, preferably made of a noble metal. The bottom electrode is covered with a layer of ferroelectric dielectric material. The ferroelectric dielectric is annealed with a first anneal prior to depositing a second electrode layer comprising a noble metal oxide. Deposition of the electrically conductive top electrode layer is followed by annealing the layer of ferroelectric dielectric material and the top electrode layer with a second anneal. The first and the second anneal are performed by rapid thermal annealing.

Process for producing high quality PZT films for ferroelectric memory integrated circuits

A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with {0001} texture provides a smooth surface for growth of {111} textured iridium, which exhibits the face-centered cubic ('FCC') structure. This seeding technique results in {111} textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports {111} textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM&#xae; memory and other microelectronic devices.

Method for producing crystallographically textured electrodes for textured PZT capacitors

A bottom electrode structure and manufacturing method is described for producing crystallographically textured iridium electrodes for making textured PZT capacitors that enables enhanced ferroelectric memory performance. The use of seed layers originating from hexagonal crystal structures with &lcub;0001&rcub; texture provides a smooth surface for growth of &lcub;111&rcub; textured iridium, which exhibits the face-centered cubic (&ldquo;FCC&rdquo;) structure. This seeding technique results in &lcub;111&rcub; textured iridium with a small surface roughness relative to the film thickness. The highly textured iridium supports &lcub;111&rcub; textured PZT dielectric layer growth. Textured PZT exhibits enhanced switched polarization, reduced operating voltage and also improves the reliability of PZT capacitors used in FRAM&reg; memory and other microelectronic devices.

A platinum deposition method uses a combination of an oxide adhesion layer and a high temperature thin film deposition process to produce platinum bottom electrodes for ferroelectric capacitors. The platinum bottom electrode is deposited onto a TiO layer at temperatures between about 300 and 800&deg; C. Deposition at high temperatures changes the platinum stress from compressive to tensile, increases platinum grain size, and provides a more thermally stable substrate for subsequent PZT deposition.

High temperature deposition of Pt/TiOx for bottom electrodes

A ferroelectric thin film capacitor and a method for producing the same wherein the capacitor dielectric includes multi-layered crystallographic textures. An integrated circuit device, such as a non-volatile memory device, includes at least one capacitor having a top and bottom electrode thereof and a ferroelectric dielectric layer therebetween. The ferroelectric dielectric layer comprises a first ferroelectric layer having a first crystallographic texture forming a main body of the dielectric layer and a second ferroelectric layer having a second differing crystallographic texture forming an interface layer between the main body and one of the top and bottom electrodes.

Ferroelectric thin film capacitors having multi-layered crystallographic textures

A ferroelectric memory cell includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and a local interconnect electrode formed on the encapsulation layer.

Capacitively coupled ferroelectric random access memory cell and a method for manufacturing the same

A charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer, wherein the dielectric layer is an encapsulation layer, and a ferroelectric memory cell includes the charge storage capacitor.

Charge pump or other charge storage capacitor including PZT layer for combined use as encapsulation layer and dielectric layer of ferroelectric capacitor and a method for manufacturing the same

Growing community of inventors

Colorado Springs, CO, United States of America

Glen Richard Fox