International Business Machines Corporation

Other

Glen R Mitchell

Roy L Hoffman

Frank G Soltis

Merle E Houdek

Douglas M Kindseth

Bruce Oliver Anthony, Jr

Larry Wayne Loen

Phillip C Schloss

William G Kempke

Richard G Mustain

James Gregory Ranweiler

Lawrence Dean Whitley

Jon H Peterson

Glenn Darrell Batalden

Thomas J Beacom

Eugene R Jones

Robert W Collins

David K Wells

In a processor having a real address space larger than its virtual address space, all of the physical memory is addressed by using a separate prefix register associated with each of the address registers to hold both a high-order address portion and a control bit specifying whether the address is to be translated or used as a direct real address.

Directed address generation for virtual-address data processors

Two different data-processing systems are interconnected into a composite system by a shared memory in the address space of each, and by a virtual channel which generates interrupts so that each system can control the other. Each system can execute standalone programs. In addition, one of them acts as an emulated terminal for the other, and also as a system console for the other.

Composite data-processing system using multiple standalone processing

An apparatus provides synchronization for page replacement control in a paged, virtual memory environment in which either the CPU or the I/O devices may pin and unpin pages to control their replacement by the paging supervisor. Pinning and unpinning of pages by the I/O devices occurs independently of pinning and unpinning performed by the CPU. Synchronization is achieved by means of a virtual address translation mechanism which is common to the CPU and the I/O devices. The virtual address translation mechanism includes a primary directory having entries for each page in main storage, with each entry containing a field in which the pinning and unpinning operations by the CPU and the I/O devices are registered. In particular, this field is a counter which is incremented when a page is pinned by either the CPU or an I/O device and decremented when a page is unpinned. Each page directory entry also includes a field for indicating that references to the page corresponding to a given page directory entry are invalid. When it is determined that a particular page is no longer in use and is eligible for replacement, the page directory entry is set to indicate that further references to the page are invalid. When an I/O device gives up a buffer page, that page is unpinned. Buffer pages newly acquired by the I/O device are pinned when they are acquired by the device and have become available in main storage.

Synchronizing mechanism for page replacement control

Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.

Virtual addressing apparatus employing separate data paths for segment

Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.

Tagged pointer handling apparatus

A circuit and process for controlling access to a digital storage device is disclosed. The process involves reading a control word from a control store and partially decoding an address field of the control word to predict the storage location to be accessed. The address field is subsequently fully decoded to determine the actual storage location to be accessed. Prior to completion of this decoding step, an access to the predicted location in main storage is initiated. In the event the actual storage location to be accessed differs from the predicted one, the memory access previously initiated is overridden and an access to the actual storage location is initiated. A digital compouter system incorporating a circuit for carrying out this process exhibited significantly reduced running times for typical computer programs.

Access-time reduction control circuit and process for digital storage

Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses a page directory having a next real address and an associated virtual address ordered according to real addresses. This simplifies the manner in which the input/output (I/O) handles addressing in a virtual storage computer system. When the I/O device control mechanism needs to resolve the real I/O address register, it uses the contents of that register to index into the page directory to obtain a corresponding virtual address. The corresponding virtual address is incremented and converted to a real address which is used to index into the page directory. The virtual address taken from the page directory is then compared with the virtual address which had been incremented and translated. If the two compare then the real address which had been used to access the page directory is entered into a register so as to be available as a real main storage address. In actuality it is only a partial real main storage address and is concantenated with a byte identifier portion of the main storage address which requires no translation and which was a part of the original I/O real address for main storage.

Address translation apparatus

A solar powered apparatus for changing water to hydrogen and oxygen gases; the apparatus including a solar powered, heat exchanger driving a turbine which turns a D.C. generator from which negative and positive electrodes extend into an electrolysis tank containing water, and gas collecting above each electrode being connected to either a hydrogen or oxygen storage tank.

Solar energy operated hydrogen refining process

The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.

Hash index table hash generator apparatus

Address translation apparatus is provided where the address to be translated is compared with two address translation candidates sequentially. The virtual address to be translated is contained in a virtual address register. A field of bits within the virtual address are presented simultaneously as an address to a translation table and a pre-translation table where the pre-translation table has two entries per row and each entry contains some of the virtual address bits of corresponding candidates in the translation table. The pre-translation table is quite narrow compared to the translation table and is preferably, but not necessarily, implemented in latches or as a very fast array compared to the translation table. The selected entries from the pre-translation table are compared with corresponding bits from the virtual address register and the results of the precompare generate an address bit which together with the other address bits select the candidate from the translation table which is more likely to compare with a larger group of address bits from the virtual address register. In the event both entries from the pre-translation table compare with the corresponding bits from the virtual address register and the selected candidate from the translation table does not compare with the larger group of address bits from the virtual address register, the address bit from the precompare is forced to an opposite state whereby the other candidate is selected.

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Pine Island, MN, United States of America

Glen R Mitchell