Sperry Corporation

Unisys Corporation

Glen R Kregness

Peter B Criswell

Clarence W DeKarske

Gary J Lucas

Lawrence R Fontaine

Ferris T Price Deceased

Kenichi Tsuchiva

Walter L Quinton

A method and apparatus for granting exclusive access to a selected portion of addressable memory to a requesting processor in a large scale multiprocessor system. An instruction processor having a store-through operand cache executes an instruction requiring exclusive access to an address in a shared memory. If the address upon which the lock is requested is not in the local cache, the instruction processor simultaneously sends a lock and read request to the coupled storage controller. Otherwise, a no-operand-read and lock request is sent to the storage controller. If, while processing the lock request, no conflict is detected by the storage controller, the address is marked as locked and a lock granted signal is issued to the requesting processor. Concurrent with the processing the lock request the storage controller processes the read request. The lock granted signal and requested data are returned to the requesting processor asynchronously. The requesting processor can continue processing the lock instruction when the lock granted and required data have been returned from the storage controller. When two or more processors contend for a lock on a the same portion of addressable memory, one processor is granted the lock while the other contending processor(s) are forced to wait. Lock contention is arbitrated by a round robin priority scheme.

Apparatus and method for controlling exclusive access to portions of

In a plural processor data processing system, a lock is obtained on a commonly shared storage means that allows for the testing of a control word associated with a selected memory address of a particular data processor wherein each of the data processors of the system is capable of independently requesting a lock on said control word. Lock requests are broadcast to each of the data processors. The lock is then established according to predefined criteria by transmission of the lock requests of all of said processor means at the same time at controlled intervals, and by providing the lock on the control word when the requesting processor is the only processor that is requesting a given control word during a control interval, or when the processor transmits its lock request simultaneously with other processor means of a lower priority.

Storage locking control for a plurality of processors which share a

A left justification scale factor generator is described which is capable of scaling numbers for binary number groups off one, two, three and four bit groups. Two basic building block circuits are utilized in the scale factor generator's priority encoder, which looks at four binary bits and produces a two bit binary count that corresponds to the first non-zero input found, and an algebraic priority encoder which also receives a reference signal that allows it to indicate the significance of the priority detection level. By sensing correction factors at the first level of the system, the number of logic levels are kept to a minimum.

Multi-function scaler for normalization of numbers

A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting system provides field selection and justification together with the capability of complementing and magnitude generation of the selected fields. Floating-point operands in two different floating-point formats can be unpacked, that is the characteristic separated from the mantissa and properly aligned, and can be packed by positioning and recombining the characteristic with that associated mantissa. Throughout the entire reformatting process, parity for selected bit groupings is maintained, thereby allowing through checking of reformatting operations. The reformatting system includes programmably selectable constant generation.

Programmable data reformat system

An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares and mask substitute operations without adding logic levels to the arithmetic logic unit; (2) the inclusion of a sum minus one network to speed up system performance by minimizing the delay usually associated with group borrow input to final sum output and (3) the inclusion of a mode control register internal to the arithmetic logic unit to minimize or camouflage the delay always found in the mode switching control of contemporary arithmetic logic units.

Masked arithmetic logic unit

A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is additionally provided to regenerate original source parity from the matrix outputs for use in thru checking. A single 9-bit parity generator is all that is required to check the correctness of the matrix.

Error checked high speed shift matrix

A high speed multiplier circuit is disclosed which not only provides increased performance for the multiply operations of a large scale processor but also provides for single bit error detection of results as well. It incorporates a gated carry/save adder array to eliminate the decoding of multiplier characters thereby reducing logic levels and enhancing performance. A means is illustrated for detecting single bit errors without redundancy or performance loss. While the array proper is more complex than other multibit algorithms, the multiplexers needed by those earlier systems are no longer required. The small increase in complexity of the array proper eliminates the need for decoding of the multiplier bits or other interaction between the multiplier groups. The net effect is a reduction in logic with faster operation because of the omission of the decoding requirement.

Fast error checked multibit multiplier

A characteristic adder for use in a data processing system that performs floating-point arithmetic operations is described. A 1's complement subtractive adder is shown for forming the sum or difference of a pair of exponents under control of function control circuitry, along with an indication of which characteristic is larger for selecting which mantissa operand should be shifted for proper alignment. The function control circuitry responds to function signals to select addition or subtraction, provide the magnitude or complement of the results, and select between two available floating-point formats. Characteristic Overflow and Underflow is tested and signaled for each of the two possible floating-point formats.

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Minnetonka, MN, United States of America

Glen R Kregness