National Instruments Corporation

Glen O Sescila, Iii

Brian Keith Odom

Kevin L Schultz

Craig M Conway

Rafael Castro Scorsi

Brent C Schwan

Neil S Feiereisel

Andrew B Moch

Aaron T Rossetto

M Dean Brockhausen, Jr

Sundeep Chandhoke

A network interface peripheral device (NIP) may include a network interface for communicating with a network, and an interconnect interface for communicating with a processor subsystem. First buffers in the NIP may hold data received from and/or distributed to peer peripherals by the NIP, and second buffers may hold payload data of scheduled data streams transmitted to and/or received from the network by the NIP. Payload data from the data in the first buffers may be stored in the second buffers and transmitted to the network according to transmit events generated based on a received schedule. Data may be received from the network according to receive events generated based on the received schedule, and distributed from the second buffers to the first buffers. A centralized system configuration entity may generate the schedule, manage configuration of the NIP, and coordinate the internal configuration of the NIP with a network configuration flow.

Direct network access by a memory mapped peripheral device for scheduled data transfer on the network

Provided in some embodiment is a computer system, including a first peripheral device, having a first external data input, a first peripheral storage device to store the measurement data, a first peripheral device output to couple to a system interconnect of the computer system. The first peripheral device capable of receiving measurement data via the external data input the first peripheral device capable of transferring at least a portion of the measurement data to a second peripheral device of the computer system via the system interconnect, and where the second peripheral device is capable of processing at least a portion of the measurement data transferred to the second peripheral device.

Peripheral devices integrated into a processing chain

Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.

Data movement system and method

A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.

Optimizing the responsiveness and throughput of a system performing packetized data transfers

Method and apparatus for optimizing the responsiveness and throughput of a system performing packetized data transfers using a transfer count mark

A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.

PCI bus to IEEE 1394 bus translator

PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching

PCI bus to IEEE 1394 bus translator employing write pipe-lining and

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Pflugerville, TX, United States of America

Glen O Sescila, Iii