Intel Corporation

Other

Glen N Wada

Krishna Kumar Parat

Albert Fazio

Gregory E Atwood

Neal R Mielke

Daniel N Tang

Anthony Ozzello

Raghupathy V Giridhar

Yudong Kim

Daniel Xu

Mansour Moinpour

Cheng C Hu

Ken Schatz

R V Giridhar

Jan V Shubert

Yang-Chin Shih

Murray L Trudel

David Albaum

Jeff Inokuchi

Denis Kitayama

Ray Wong

Brian Komoto

Gerald Yin

Don W Jillie, Jr

A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

Integrated memory cell and method of fabrication

A method for making a flash memory having a passivation layer that is not transparent to ultraviolet light. The method forming a semiconductor that includes flash memory cell having floating gate, then forming a the substrate. Process induced charge that has accumulated on the flash cell floating gate is then neutralized and a passivation layer, which is no transparent to ultraviolet light, is formed on the conductive layer.

Flash memory with UV opaque passivation layer

A method of passivating an integrated circuit comprising providing an integrated circuit having a top side including a bond pad, depositing a first dielectric over said top side of said integrated circuit, exposing a first area portion of a top side of said bond pad, depositing a second dielectric of one of a material that is substantially impermeable to moisture over said top side of said integrated circuit, and exposing a second area portion of said top side of said bond pad, said second area portion within said first area portion is disclosed.

Passivation for tight metal geometry

A method for making a flash memory having a passivation layer that is not transparent to ultraviolet light. The method comprises forming a semiconductor substrate that includes a flash memory cell having a floating gate, then forming a conductive layer on the substrate. Process induced charge that has accumulated on the flash cell floating gate is then neutralized and a passivation layer, which is not transparent to ultraviolet light, is formed on the conductive layer.

Method for making flash memory with UV opaque passivation layer

A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.

Method of fabrication of a novel flash integrated circuit

The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

Self-aligned contact process in semiconductor fabrication and device therefrom

A system and method for ordering and prescribing drugs for a patient. This system includes an improved process for facilitating and automating the process of drug order entry. The user may interact with the system in a variety of ways such as keyboard, mouse, pen-base entry or voice entry. The system includes a database containing medical prescribing and drug information which is both general and patient-specific. The system also permits the user to view current and previously prescribed medications for any patient. The system can alert the user to potentially adverse situations as a result of the prescribed medication based on information in the database. The system also can automatically determine product selection based on descriptions and can automatically communicate the order to a pharmacy. Further, the system includes a means for automatically displaying messages to the user relating to predetermined situations. For example, such situations may include a medication which is not available in the formulary or the prescription of a non-recommended medication. The system streamlines the order entry process and makes information important to the drug ordering process easily available.

Interactive medication ordering system

Self-aligned contact process in semiconductor fabrication

A process for fabricating ultra-high density (e.g., 64Mbit) contactless EPROMs and/or flash EPROMs in a silicon substrate is described. Spaced-apart island members are formed of poly 2/ dielectric/poly 1 layers over gate oxide regions. Each island member is associated with one of the cells within the array, and is separated from each other by trenches extending down to either the field oxide or substrate regions. Elongated, parallel, spaced-apart source/drain regions are formed on adjacent sides of the channel regions by ion implantation. The trenches are then filled with an insulating material and a plurality of wordlines patterned across the array. Each wordline makes electrical contact to the control gate members associated with the single row of cells within the array.

Process for fabricating a contactless floating gate memory array

A method for etching of metal-oxide-semiconductor (MOS) devices utilizing a multi-step power reduction plasma etching recipe to reduce ion bombardment damage on the resulting surface. The multi-step power reduction recipe allows for reasonable throughput of wafers due to a relatively high etch rate at the upper layers of the surface followed by progressively lower power corresponding lower etch rates at the lower levels of the surface. The etching process is followed by a cleaning process to remove metallic contamination resulting from the plasma etching process to yield an excellent surface for growing low defect density MOS gate oxides with high dielectric integrity.

Plasma etching process for MOS circuit pregate etching utiliizing a

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Fremont, CA, United States of America

Glen N Wada