Applied Micro Circuits Corporation

Glen Miller

Dimitrios Giannakopoulos

Ravi Subrahmanyan

Tracy Ma

Timothy P Walker

Xingen (James) Ren

Xingen James Ren

Armin Schulz

Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Self-test design for serializer / deserializer testing

System and methods are provided, in an Optical Transport Network (OTN), for communicating asynchronous Tributary Slots (TSs) via a synchronous Optical Payload Transport Unit of level k (OTUk) interface. The transmission method accepts a plurality of TSs at a corresponding plurality of asynchronous data rates. The TSs are mapped, using a tangible memory medium, into pseudo-Optical channel Data Tributary Unit (ODTU) frames synchronized to a common clock. Then, the synchronized pseudo-ODTU frames can be interleaved into an OTUk frame, without the need of a phase-locked loop (PLL) or buffering.

Transporting asynchronous ODUk signals over a synchronous interface

System and method for transporting asynchronous ODUk signals over a synchronous interface

A system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method provides information bytes at a nominal system clock-based data rate, which is about equal to a system clock, but may be adjusted. An external clock has a rate approximately equal to the system clock rate. The method generates SPEs with identically-positioned information bytes, regardless of differences between the system and external clock rates. The SPEs are combined with Transport Overhead (TOH) and transmitted as a message frame at the external clock rate. SPEs are generated maintaining the positions of the information bytes within each SPE, without pointer adjustments, despite differences between the system and external clock rates. Expressed another way, message frames are generated with payload and TOH sections, and the information bytes are located exclusively in the payload sections. As a result, constant pointer values (e.g., H/Hor V/V) are maintained for all the SPEs.

Synchronous payload envelope mapping without pointer adjustments

System and method for synchronous payload envelope mapping without pointer adjustments

A ring connection system and method are providing for distributing signals in an optical-to-electrical interface. The method electrically connects a plurality of nodes in a series-connecting ring, and receives an optical signal at a first node from a service provider. The method converts the optical signal to an electrical signal, and distributes the electrical signal via the ring. At each node, the electrical signal is supplied from a customer interface. Typically, each node has a plurality of customer interfaces. In one aspect, ITU-T G.984.3 Giagbit-capable Passive Optical Network (GPON) optical signals are received converted to a customer interface electrical signal such as an Ethernet connecting transfer mode, or time division multiplexed signal. Electrically connecting the plurality of nodes in the series-connected ring includes: series connecting the nodes in a North ring; and, series connecting the nodes in a South ring, opposite in direction from the North ring.

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Haverhill, MA, United States of America

Glen Miller