Motorola Corporation

Glen James Zoerner

Hing Leung Yiu

Kevin B Traylor

John Richard Oakley

Ralph E Snowden

Wendy Reed

Jeff Gokinko

Danny H Nguyen

Wai-Kin Steven Kwan

Andrew Chu

On Ki Chu

A method and apparatus for applying patches to a code or data residing on a non-volatile memory device is illustrated. A code residing at a first location in a non-volatile memory can be replaced by a codes residing at a second locations in a memory map. A patching device compares a first address of a first code to an address identified by a pre-fetch instruction. If the first address matches the address identified by the pre-fetch instruction, a pre-fetch abort is issued to facilitate replacing a bad code residing at the first address with a good code. The good code can be pointed to by a vector in a vector table where the address of the vector is dynamically loaded into a program counter.

Method and apparatus for patching code and data residing on a memory

A data processing system (20) has a display controller (28) that uses bus arbitration and data bursting to supply display data for refreshing an LCD screen (49), utilizing a system memory (30) instead of a separate video RAM. A screen DMA (58) fills a line buffer (60) with display data from the system memory (30) in bursts of a predetermined number of words. The screen DMA (58) receives a faster clocking signal than is used by the CPU (22). This allows the screen DMA (58) to run faster than the CPU (22) to reduce bandwidth needed to retrieve the display data. In addition, if the CPU (22) clock frequency is changed for power management purposes, the LCD screen (49) is not affected since it uses a different clock. By using the system memory (30) for storing display data, pin count, packaging costs, and board space are reduced.

Data processing system having display controller with bursting direct

When an external reset signal EXRST is asserted received by a reset unit (6), it is synchronised with an internal clock to produce an internal reset signal INRST, which is applied to a CPU (4) and other modules in the circuit to reset them. While the internal reset signal INRST is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller (7) for refreshing data in DRAM (3) is increased. Then, when the external reset signal EXRST is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller (7) so that it is reset. The CPU, being already reset, can then quickly reconfigure the DRAM controller and re-enable it to resume refreshing the DRAM (4), thus maintaining the data in the DRAM.

Circuit and method for retaining data in DRAM in a portable electronic

A data processing system (20) has a multi-function scalable parallel I/O port (44). The I/O port (44) includes a plurality of I/O port circuits (55, 56) coupled to I/O terminals (67, 77) . The I/O port (44) can multiplex two functions onto one terminal (67,77) . One function is an I/O function and the other function is function under the control of an internal module (22, 24, 26, 32) connected to the terminal (67, 77). Each I/O port circuit (55, 56) has either a pull-down circuit (68) or a pull-up circuit (78) coupled to the terminal (67, 77). The pull-up and pull-down circuits (78, 68) are controllable using a control register (81, 82). The pull-up and pull-down circuits (78, 68) for each terminal (67, 77) can be individually selected, and function whether the I/O port (44) is selected or deselected.

Data processing system having a multi-function input/output port with

A method for testing a phase locked loop (103) within an integrated circuit (100) is performed by utilizing an on-chip timer module (100) as a frequency counter (121) for counting the number of clock pulses outputted from the phase locked loop circuit (103) over a selected time period. The test is performed by an external testing device (111) having access to the address/data bus (110) coupled to both the phase locked loop circuit (103) and the timer module (109).

System and method for testing a phase locked loop in an integrated

An electronic switch for supplying power to a digital telephone which consumes substantially no power in the idle mode. A transistor for supplying power to the digital telephone is latched on in either of two situations. In the first situation, the telephone's hookswitch is closed. A second transistor turns on and maintains the first transistor on even after the hookswitch has been opened. In the second situation, a voltage pulse is applied to the input voltage conductor lines causing the first and second transistors to turn on. Again, the second transistor maintains the first transistor on. The circuit is inactivated by a sleep signal which turns off the second transistor which in turn turns off the first.

Growing community of inventors

Austin, TX, United States of America

Glen James Zoerner