Infinite Technology Corp.

Glen Haas

George H Landers

Tim B Smith

Earle Jennings

A reconfigurable processor includes at least three (3) MacroSequencers (,)-(,) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (,) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (,) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (,) is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units. An instruction memory (,) contains an instruction word that is operable to control configurations of the datapath through the execution units for a given instruction cycle. This instruction word can be retrieved from the instruction memory (,), the stored instructions therein sequenced through to change the configuration of the datapath for subsequent instruction cycles.

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Glen Haas