Micron Technology Incorporated

Micron Display Technology, Inc.

Micro Technology, Inc.

Nan Ya Technology Corporation

Micron Semiconductor, Inc.

Micron Display

Lodestar Licensing Group LLC

Glen Earl Hush

Richard Cameron Murphy

Honglin Sun

Timothy P Finkbeiner

Fa-Long Luo

Aaron Preston Boehm

Troy A Manning

Perry Victor Lea

David A Cathey

Anton Korzh

Jason T Zawodny

Mirmajid Seyyedy

John K Lee

Vijay S Ramesh

James J Hofmann

Allan Kennedy Porterfield

Kunal R Parekh

Stephen L Casper

Sean Stephen Eilert

David L Pinney

Aliasger Tayeb Zaidy

Jake Baker

Mark E Tuttle

Mark R Thomann

Troy D Larsen

Huy Thanh Vo

David A Zimlich

Jeremiah James Willcock

Jonathan D Harms

Thomas W Voshell

Jun Liu

John T Moore

Kevin G Duesman

Mike P Violette

Patrick A La Fratta

Mark D Ingram

Shivam Swami

Naveh Malihi

Manoj Sinha

Craig M Dunham

Jesse F Lovitt

Tyler A Lowrey

R Jacob Baker

Daniel B Penney

Harish Naga Venkata

Manny K F Ma

Guy S Perry

Jeffrey P Wright

Manny K Ma

Eugene H Cloud

Robert R Rotzoll

Dean Andrew Wilkinson

Zhong-Yi Xia

James J Cathey

Steve Casper

Steven Howell

Tom W Voshell

Jeffrey S Mailloux

Kristopher Kopel

Glenn W Piper

Russell J Baker

David A Carthey, Jr

Mark Thomman

William Lewis

Terry C Vollman

David W Overgaard

Andrew P Lyle

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

Apparatuses and methods for parallel writing to multiple memory device structures

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.

Testing memory of wafer-on-wafer bonded memory and logic

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

Signal routing between memory die and logic die for performing operations

Apparatuses and methods can be related to implementing a conditional write back scheme for memory. The data may be stored by memory cells of a memory array. The data may be moved to sense circuitry. The data can be conditionally held by the sense circuitry while a plurality of operations is performed. The results of the plurality of operations can dictate whether to commit the data to the memory cells.

Conditional write back scheme for memory

Apparatuses and methods related to mitigating unauthorized memory access are described. Mitigating unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then a row of the memory array corresponding to the access command may not be activated.

Unauthorized memory access mitigation

Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

Apparatuses and methods for ordering bits in a memory device

Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

Apparatuses and methods for organizing data in a memory device

Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device. In some examples, the processing circuitry may include an analog-to-digital conversion capability for digital communication of analog characteristics internal to the memory die.

On-die testing for a memory device

The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

Logical operations using memory cells

The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

Apparatuses and methods for operations in a self-refresh state

A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

Signal routing between memory die and logic die

A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

Memory device for wafer-on-wafer formed memory and logic

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

Signal routing between memory die and logic die for mode based operations

Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator.

Supplemental AI processing in memory

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

Apparatuses and methods for data movement

Growing community of inventors

Boise, ID, United States of America

Glen Earl Hush