Honeywell International Inc.

Staktek Group L.p.

Dpac Technologies Corp.

Stuktek Group L.p.

Glen E Roeters

Andrew C Ross

Richard J Pommer

Harlan R Isaak

Boris Moldavsky

Frank E Mantz

Stephen M Avery

Raj Kumar

John Patrick Sprint

Joel Andrew Mearig

Jim Yardley

A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrically connected to the first conductive pattern of the flex circuit such that the integrated circuit chip packages are positioned upon respective ones of opposed top and bottom surfaces of the flex substrate. Alternatively, one of the integrated circuit chip packages may be positioned upon the top surface of the flex substrate and electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached in a non-conductive manner to the bottom surface of the flex substrate such that the conductive contacts of such integrated circuit chip package and the leads collectively define a composite footprint for the chip stack.

Stacking system and method

CSP chip stack with flex circuit

A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame. Alternatively, one of the integrated circuit chip packages may be electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached to the base substrate and at least partially circumvented by the interconnect frame such that the circumvented integrated circuit chip package and the second conductive pattern of the interconnect frame collectively define a composite footprint for the chip stack. A transposer layer may be included as a portion of each chip stack, with the transposer layer including a third conductive pattern specifically configured to provide a CSP-TSOP interface.

Panel stacking of BGA devices to form three-dimensional modules

The present invention provides a plurality of vertically stacked semiconductor dies which are electrically connected to each other. Each semiconductor die has leads which extend out from at least two opposed side surfaces of the semiconductor die. Each lead defines a first junction, a second junction, an inner width and an outer width. The second junctions of the leads of the upper semiconductor die are electrically connected to the first junctions of the leads of the lower semiconductor die. Additionally, the inner widths of the leads of the upper semiconductor die prior to electrically connecting the leads of the upper and lower semiconductor dies are less than the outer widths of the leads of the lower semiconductor die.

Thin scale outline package

A worktable that can be used to support a substrate while forming a hole therein. The worktable may include one or more actuators that stretch the substrate. The worktable may also have a control unit that is connected to the actuators and strain gauges that sense the strain in the substrate. The control unit, actuators and strain gauges may provide a closed loop control system for tensioning the substrate. The center portion of the substrate may be supported by wires that extend across an opening in the worktable. The opening eliminates a backing surface that may interfere with a laser hold forming process.

Device for controllable stretching of thin materials

A method of rinsing an electronic substrate recognizes that adding a buffer to a rinsing fluid eliminates fluctuations in the amount of residues on an electronic substrate, and a buffered rinsing fluid is prepared by (a) providing water from a water source; (b) deionizing the water to produce deionized water; (c) adding a buffer to the deionized water at a concentration effective to eliminate fluctuations in the amount of residues on the electronic substrate. The electronic substrate is rinsed with the buffered rinsing fluid.

Low species buffered rinsing fluids and method

A post in ring interconnect used for 3-D stacking. A retaining ring is formed on a pad on a bottom surface of a top PCB substrate to be stacked with a bottom PCB substrate. A post is formed on a pad on a top surface of the bottom PCB substrate. A conductive paste is applied on the pad on the bottom surface of the top PCB substrate and retained in a pocket partially defined by the retaining ring. The retaining ring is aligned with the post. By performing a compression step, a eutectic bond is formed between the top and bottom PCB substrates by the post and the conductive paste.

Post in ring interconnect using for 3-D stacking

A retaining ring interconnect. A retaining ring is formed on a perimeter of a pad on each of two adjoining surfaces of two PCB substrates. A conductive paste is applied between the pads on the two adjoining surfaces. The retaining rings are aligned and facing with each other. By performing a heat compression process, the retaining rings are connected to encompass the conductive paste. A eutectic bond is thus formed to bond the two PCB substrates.

Retaining ring interconnect used for 3-D stacking

Methods and apparatus are provided which decrease the amount of movement likely to occur during processing of a substrate. In particular, a horizontally supported dielectric panel is subjected to a series of processing steps during which the panel is heated, cooled, or maintained at a fixed temperature so as to a achieve a 2 to 1 reduction in material movement during subsequent processing. It is contemplated that application of the disclosed methods to a dielectric panel will be particularly beneficial when application is accomplished prior to laser drilling and sputtering the panel.

Removing inherent stress via high temperature annealing

An automated tool that can handle a sheet. The tool may include a flexible membrane that is attached to a frame. The flexible membrane may include a vacuum opening that is adapted to pull the sheet into the membrane. The vacuum opening may pull the outer edges of the sheet out of a tray when the membrane is deflected to a flat position. The tool may then move away from the tray wherein the outer edges of the membrane and sheet are pulled from an adjacent sheet. This effectively &ldquo;peels&rdquo; the sheet out of the tray.

Vacuum device for peeling off thin sheets

A method for coating substrates having sides of the substrate with unequal adhesion properties includes the steps of non-symmetrically coating the substrate by coating a first side under a first set of coating conditions and coating a second side under a second set of operating conditions wherein the operating conditions used to coat each side are varied so as to compensate for the unequal adhesion properties of the sides. Also, a method for substrate preparation comprising the steps of: providing an annealed thermoplastic substrate base layer having a first surface and a second surface; stabilizing the substrate base layer in an environment having a baseline temperature and relative humidity; drilling vias in the base layer; subjecting the first and second surfaces of the base layer to ion processing so as to remove contaminants caused by drilling the vias and to prepare the first and second surfaces for sputtering; metalizing the base layer by first sputtering at least one metal layer onto the first surface of the base layer and subsequently sputtering at least one metal layer onto the second surface of the base layer said sputtering of the metal layers being controlled so as to prevent the temperature of the base layer from exceeding the annealing temperature of the base layer; allowing the metalized base layer to stabilize in an environment having the baseline temperature and relative humidity and then subjecting the metalized base layer to further processing so as to modify the metal layers into conductive patterns.

Growing community of inventors

Huntington Beach, CA, United States of America

Glen E Roeters