Hewlett-packard Development Company, L.p.

Glen Douglas Dower

Peter Andrew Seiler

Christopher Ritchie Tabarez

Mark Lessman

Neill Thomas Kapron

Nicolas James Jurich

Stephen G Uhlmann

A compute system includes a security processor, a component, a component memory, a first communication link, and a second communication link. The component memory stores machine readable instructions executable by the component. The first communication link communicatively couples the component memory to the security processor. The second communication link communicatively couples the component memory to the component. The security processor is to cryptographically authenticate the machine readable instructions stored in the component memory in a boot process.

Compute systems including a security processor

A read-only memory (ROM) stores firmware code for a hardware component. A firmware controller is directly physically connected to the hardware component and to the ROM. The firmware controller exposes a virtual ROM link to the hardware component. The hardware component accesses the firmware code over the virtual ROM link exposed by the firmware controller.

Component access to ROM-stored firmware code over firmware controller exposed virtual ROM link

In an example in accordance with the present disclosure, a system is described that includes a hub for routing data traffic between a first computing device and a second computing device. A detection device of the system detects a communication protocol between the computing devices. A switch of the system routes traffic directly between the computing devices when a first communication protocol is detected. When a second communication protocol is detected, the switch re-routes traffic of the first type from the first computing device back to the hub to convert the traffic of the first type to a second type and routes converted traffic directly to the second computing device.

Routing and converting traffic based on communication protocols

An example of a controller for bus endpoint isolation can include an interface to couple to a bus that has respective communication channels and respective switches corresponding to endpoints of the bus, a processing resource, and a memory resource storing non-transitory instructions executable by the processing resource to select a first endpoint of the endpoints to receive a message from the interface via a first switch on a first communication channel associated with the first endpoint, cause, via a switch control mechanism, a second switch associated with a second endpoint of the bus to open to isolate the second switch; and responsive to causing the second switch to open, send the message via the first communication channel and the first switch to the first endpoint.

Bus endpoint isolation

Input/Output port configurations using multiplexers are described herein. An example computing system includes a multiplexer having a first input, a second input, and an output. The computing system also includes a first channel connecting the first input to a first host controller, the first host controller to transfer data at a first speed, and a second channel connecting the second input to a second host controller, the second host controller to transfer data at a second speed higher than the first speed. The example computing system further includes a third channel connecting the output to a port, the port to receive a connector of an electronic device, and a line selector to, based on a type of the electronic device connected to the port, configure the multiplexer to electrically couple the output to the first input or the second input.

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Ft. Collins, CO, United States of America

Glen Douglas Dower