Apple Inc.

Glen D Stone

David V James

Donald N North

Peter W Fletcher

A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

System for and method of efficiently controlling memory accesses in a multiprocessor computer system

A method and system for providing cyclic redundancy check (CRC) functions within a ringlet-type interconnect of a computer system are described. By time multiplexing CRC checking and generating functions, the number of CRC units can be reduced.

Time multiplexing of cyclic redundancy functions in point-to-point ringlet-based computer systems

A multiple function peripheral connecting device that allows more functionality in the limited port space of a computer is disclosed. The connecting device provides the capability for external devices having different functions to be connected to the computer through a single port. This is accomplished by wiring a first function, internal to the computer, to certain pins of a modular connector, and wiring a second function, also internal to the computer, to a certain different combination of pins on the same modular connector. Because differently sized plugs can fit with the modular connector, peripherals associated with different types of systems can connect with the computer through the same single jack. Also, an adapter may be connected to the computer to allow simultaneous use of the two internal functions.

Method and apparatus for connecting peripherals having various size

A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing request packets over the split-response bus. The method and system includes providing precedence information in the request packets, and then using the precedence information when receiving the request packets to determine which request packets to process and which request packets to reject when a conflict occurs.

Method and system for avoiding starvation and deadlocks in a

A system and method for coordinating the transmission and receipt of large data blocks as a series of smaller burst transfers through an intermediate interconnect coupling a pair of devices. A device receiving a transaction request ('initiator') specifies the data block size of the requested transaction to the other device ('target'). The target response will indicate that it is committed to the transaction, that it does not support requested transactions of the specified data block size, or that it currently lacks the buffer capacity to commit to the requested transaction. In the first instance, the initiator and target exchange the data block through the interconnect as a series of burst transfers until all data has been transferred, at which time the initiator (for read transactions) or the target (for write transactions) forwards the transferred data as a data block of the specified size. When the response indicates the target supports only smaller data block sizes, the initiator may adjust the specified data block size accordingly and proceed with the transaction once the target is committed. When the target response indicates insufficient buffers are currently available to accommodate data of a supported block size, the transaction may proceed as a series of independent burst transfers until all data is transferred or buffers sufficient for the specified block size become available.

System for transferring data specified in a transaction request as a

System for an method of efficiently controlling memory accesses in a

A system and method for multicasting control signals to selectively operate one memory device or groups of memory devices comprises a memory controller coupled to a plurality of memory devices by a command bus and a data bus. Each of the plurality of memory devices has a unique identification number. The system provides an addressing scheme in which an individual memory device or groups of memory device can be selected for operation by addressing the devices with a command packet. The memory controller broadcasts a command packet over the command bus to the plurality of memory devices. The packet includes an identification number. At each of the memory devices, selection logic is included to make the memory device operational if the identification number in the packet matches the identification number assigned to the memory device. The address in the packet is preferably encoded such that identification number has the same size regardless of whether a single memory device is being selected for operation or a group of memory devices are being selected for operation. The present invention also includes a method for selecting groups of memory devices for operation by multicasting a select address comprising the steps of: providing an memory identification number to each memory device, transmitting an memory device selection address, comparing the memory device selection address to the memory identification number, and asserting a signal to make the memory device operational if the memory device selection address and the memory identification number match.

Multicasting system for selecting a group of memory devices for operation

A system for efficiently supporting critical-word-first data transfers comprises a data storage device, a controller, a data selector, and a multiplexer. The data storage device is preferably capable of outputting data in one or more word orderings. The controller is preferably a state machine that processes data transfer requests by determining the orderings of data that the associated data storage device, data selector and multiplexer can provide, determining the ordering for the data requested and creating a response packet with the data ordered in critical-word-aligned order beginning with the word containing the requested address. The present invention also includes a method for efficiently supporting critical-word-first data transfers. The method includes the steps of: monitoring the bus for a data request packet; determining the desired order for the requested data; determining the transmission orders in which the data storage device can provide the data; determining the transmission order best matching the requested order and creating a response packet with the data ordered in the order best matching the desired requested order; adding response format information to the header of the response packet and transmitting the response packet on the bus.

System for generating and sending a critical-world-first data response

A method and system for efficiently routing data packets in a computer interconnect includes a plurality of nodes forming a ringlet, generally including two connections between each pair of nodes configured to allow communication in either direction between each pair of nodes. One sequence of such connections forms a run moving,-for example left-to-right between a series of nodes. The other sequence of connections forms a right-to-left run. Selected nodes are configured to provide two cross-over paths, each from one run to the other, so the two runs are linked to form a circle or ringlet. One or more selected nodes provide an optional connection between the two runs, thus allowing a fast path or short cut to the opposing run. A fast path may include a uni- or bidirectional cross through path in an intermediate node. In one preferred embodiment, a single node can provide both cross-over paths, but can also support a cross-between path for each run, allowing a packet to continue on the same run, rather than the default path that crosses over to the opposite run. The method and system includes data information in a packet that can be used to decide whether to switch the packet through a fast path or to let it continue on the 'normal' path. Routing decisions are based on a path field within each packet. This field is updated when taking a faster path (for example, a cross-through or cross-between path). The update techniques allow data packet path lengths to be reduced, while also providing a packet-aging capability. A scrubber is provided to manage packet aging and to remove packets that have not been removed from the ringlet but are no longer useful.

System and method for efficiently routing data packets in a computer

An apparatus for performing indivisible memory operations on memory locations in remote memory means in multiple bus, multiple processor computer systems comprises a logic supervisor coupled to a bus bridge. The logic supervisor comprises a lock address register, a buffer address register, a command register, a first parameter register, a second parameter register, a first latch, a second latch, a comparator, and a controller. The controller is a state machine that observes instruction sequences intended to create an indivisible memory operation on a remote bus. When the logic supervisor detects an indivisible memory operation instruction sequence with a remote address, it gathers the data for the indivisible memory operation, inhibits the processor, and hands the data off to the bus bridge. When the logic supervisor receives a completion status from the bus bridge it places the returned value in memory and releases the processor. Should the logic supervisor detect an indivisible memory operation instruction sequence, but not a remote address, the logic supervisor does not participate in the indivisible memory operation.

System and method for executing indivisible memory operations in

A multi-processor computer system comprising a data storage device, a memory controller, and a plurality of processors. The data storage device has a plurality of memory lines, each memory line having a portion for alternatively storing data or, a set of GONE codes, a count value, and a processor identification code value. A memory controller coupled to the data storage alternatively stores and retrieves data or the GONE code, the count field value and the processor identification code value. At least one of the processors includes a cache memory and a cache memory controller. The cache memory controller compares a GONE code associated with the requested memory line with the contents of the requested memory line, and requests the contents of the requested memory line from a second of the processors in response to the comparison.

System and method for preventing stale data in multiple processor

An elasticity buffer for use in a data transmission system having a transmitter and a receiver and utilizing a data transfer protocol that periodically supplies an elasticity element that can be deleted or replicated by the elasticity buffer to maintain the synchronous transfer of data elements. The elasticity buffer includes: a memory array and at least one flag per memory location operative to be set to a first or second state; a write controller operating at the transmitter clock for writing the data elements into the memory locations in a sequential order and setting the corresponding flags; a read controller operating at the receiver clock for reading the data elements from the memory locations in the sequential order; and a flag controller for reading the flags, determining if the transmitter clock is faster or slower than the receiver clock from the pattern of flags read from memory, communicating a delete signal to the read controller to delete an elastic symbol if the transmitter clock leads the receiver clock, and communicating a replicate signal to the read controller if the transmitter clock lags the receiver.

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San Jose, CA, United States of America

Glen D Stone