Sperry Corporation

Unisys Corporation

Sperry Rand Corporation

Glen D Rattlingourd

John W Zscheile, Jr

Billie M Spencer

Robert J Currie

Clifford T Johnson

Larry J Miller

Richard W Harris

Richard K Wells

Stanley D Moss

Willis B Adkisson

Frank A Bishop

James R Nelson

A novel low speed code sequence generator having a set of parallel flip-flops is provided and comprises a vector generator in series between the outputs and the inputs of the set of parallel flip-flops in the generator. The outputs from the low speed code sequence generator may be multiplexed together to provide an individual high speed code sequence. The selective outputs from a plurality of low speed code sequence generators may be algebraically combined and then multiplexed together to provide a composite code sequence.

High speed code sequence generator

An improved interface arrangement between an antenna controller and one or more antennas. The interface includes a reduced number of control lines but is capable of handling complete interface requirements including control and status between the antenna controller and the antenna.

Antenna interface common module

A very rapidly converging adaptive filter which uses a variable scale factor for each weight of the filter. The value of the variable scale factor is chosen for each iteration and is based upon the sign changes of the incremental weight change. The variable scale factor exhibits large values when no sign changes occur and smaller values when sign changes occur. The new filter provides considerable improvement in increase of convergence rate and decrease in residual errors even in the presence of heavy noise while requiring only a modest increase in hardware.

MSE variable step adaptive filter

An electronic system for providing a stable, isochronous clock signal with very low jitter and slew rate to thereby permit multiplexing of data from an external source which is not synchronous with the multiplexer frame rate.

Isochronous clock reconstruction

A high rate multiplexing system which is capable of operating on multiple channels while ensuring synchronization of the system operation. The system includes a basic timing network for synchronizing the system operation. Automatic phase adjusters are used to re-align data signals with a clock signal whenever data transitions occur while the data is being sampled. Synchronizing circuits are used to insert synchronization data bits into the multiplexed data streams where appropriate. A medium rate multiplexer generates two different data streams, certain clock signals and strobe signals. A higher rate multiplexer is capable of operation in different modes, including but not limited to wideband operation or narrow band operation. A Manchester encoder combines data output signals into a single aggregate data stream.

High rate multiplexer

A multiplexer system which operates as a standard multiplexer as well as a proportional multiplexer by providing typical multiplexing operation by one circuit portion and proportional multiplexing operation by other portions of the circuit wherein the multiplexer system can interface with a plurality of users or user devices in such a way that data streams between the user devices and the multiplexer system can be reallocated so as to enhance data transfer irrespective of the clock-to-data relationship such that no data is lost during circuit operation. The proportional MUX can be selectively controlled by a microprocessor.

Standard/proportional multiplexer

A novel maximum likelihood sequence detector is provided for decoding linear cyclic error correction codes. The detector comprises one cyclic correlator for each two shaft sets of the code which have weights greater than one, and a serial correlator for detecting the shift sets of all zero's and all one's. The number of cyclic correlators required to decode linear codes is reduced to less than half the number of shift sets which define all the codewords instead of half the number of codewords where the number of shift sets is always less than the number of codewords.

Maximum likelihood sequence decoder for linear cyclic codes

A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x.sup.6 +x.sup.5 +x.sup.3 +x.sup.2 +1, and x.sup.6 +x.sup.3 +x.sup.2 +x+1. The architecture of the instant decoder is appropriate for implementation on a single, monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals representative of data input signals.

Bit serial convolutional decoder for VLSI implementation

A novel interleaver-de-interleaver is provided which is adapted to store bits of a data stream after being error encoded. The data bits are stored in a random access memory in addresses identifiable by an array of columns and rows. The interleaver comprises address pointer means and logic for reading the data bits out of the memory addresses in a predetermined reordered sequence to provide a quasi-random pattern sequence of data bits which when transmitted are substantially immune to periodic bursts of radio frequency interference signals.

Apparatus for interleaving and de-interleaving data

A tri-level serial data stream and its inverted form are received and separated into data and clock for use with standard bi-level logic. The incoming tri-level signal and its inverted form are separately biased to permit a true differential comparison and signal detection. High common mode rejection of noise that is developed between a transmitter and receiver is thus provided.

Tri-level differential line receiver

An improved method of recovering a clock reference signal from digital data and maintaining small phase errors between the two. The clock reference signal is phase matched with the digital data by comparing the positive going and negative going edges of the data with the clocking edge of the clock signal. A hard decision is made on the relative phase of the clock signal and the data only after several edge transitions occur. After a finite number of samples of these transitions, a decision is made whether to advance or retard the clock signal by observing whether the majority of the data transitions over the sample period occurred prior to or after the clocking edge of the clock signal. This allows a sampled mean to be established and thereby a more accurate prediction of the relative phase between the clock signal and data to be made. In addition, a fast acquisition technique is provided to insure the clock reference signal is received in a minimum amount of time.

Digital timing recovery system

An automatic clock phase adjustment circuit is incorporated in a local unit of a data clocking system. The local unit also includes a clock pulse generator and a local data storage device. The system also includes a remote unit having a remote data storage device. The automatic clock phase adjustment circuit receives clock pulses from the generator and produces output clock pulses having first and second half periods interconnected by a clocking transition which when applied to the remote storage device causes clocking out of data to the local storage device. The circuit also produces a sampling pulse during each of the first and second half periods of the output clock pulses and is operable to detect in which particular one of the half periods a positive transition in the incoming data has occurred during the interval of a sampling pulse in that half period. This permits the circuit to produce local or input clock pulses for clocking in the incoming data at the local storage device during the other of the half periods so that the clocking edges of the input clock pulses will not coincide with any of the positive transitions of the incoming data when applied to the local storage device. As a result, reliable storage of the incoming data is guaranteed to occur at the local storage device at times when the data is stable.

System and method for clocking data between a remote unit and a local

Electronic digital apparatus for computing an approximation of the arctangent of a given tangent number, N, being in the range of 0 to 1 and in binary form, operates in two stages to provide a solution of the expression: ##EQU1## During the first stage, steps are taken by the apparatus to find out where within the range of 0 to 1, divided preferably into four equal increments, the known tangent number N is located. When the correct increment represented by one of a plurality of increment numbers I.sub.j stored in a ROM unit of the apparatus is found, then one of a like plurality of center numbers C.sub.k of that increment also stored in the ROM unit may be readily selected, as can also be the corresponding one of a plurality of stored numbers A.sub.i representing the arctangents of the stored center numbers C.sub.k. During the first stage, the product number C.sub.k (N) is also formed. In the second stage of operation of the apparatus, the dividend and divisor numbers N-C.sub.k and 1+C.sub.k (N) are first calculated. The quotient number,

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Salt Lake City, UT, United States of America

Glen D Rattlingourd