Arm Limited

Motorola Corporation

Other

Glen Andrew Harris

James Nolan Hardage

Stephen John Hill

Conrado Blasco Allue

Yasuo Ishii

David James Williamson

Mark Carpenter Glass

Abhishek Raja

William Elton Burky

Michael Filippo

Nicholas Andrew Plante

Joseph Charles Circello

Alexander Cole Shulyak

Robert Greg McDonald

Muhammad Umar Farooq

Michael Brian Schinzler

Michael David Achenbach

Bipin Prasad Heremagalur Ramaprasad

Huzefa Moiz Sanjeliwala

Jason Lee Setter

Rakesh Shaji Lal

Vasu Kudaravalli

Robert Gregory McDonald

Steven Daniel Maclean

Nicholas Todd Humphries

Li Ma

There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

Memcpy micro-operation reduction

There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

Compression of entries in a reorder buffer

A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, following instructions that appear after the status updating instruction in the instruction stream.

Speculatively executing instructions that follow a status updating instruction

A data processing apparatus is provided. It includes processing circuitry for speculatively executing a plurality of instructions. Storage circuitry stores a current state of the processing circuitry and a plurality of previous states of the processing circuitry. Execution of the plurality of instructions changes the current state of the processing circuitry. Flush circuitry replaces, in response to a miss-prediction, the current state of the processing circuitry with a replacement one of the plurality of previous states of the processing circuitry.

Storing a processing state based on confidence in a predicted branch outcome and a number of recent state changes

Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.

Data processing

A loop buffer is provided with a main storeand an auxiliary store. The main storestores micro-operation instructions. The auxiliary storehas fewer entries than the main storeand stores target addresses for predicted taken branch instructions stored within the main store. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

Buffer store with a main store and and auxiliary store

An out-of-order processorgroups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

Size mis-match hazard detection

A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural register value has a fixed bit width irrespective of the bit width of the destination operand being written thereto. Instead of adding these zero values everywhere in the data path, they are instead represented by zero flags in at least the physical registers utilized for register renaming operations and in the result queue prior to results being written to the architectural register file. This saves circuitry resources and reduces energy consumption.

Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register

A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register filecontaining architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file. A first decoderfor the first instruction set and a second decoderfor the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitryfor supporting register renaming in conjunction with a physical register fileand an architectural register file

Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format

A motor vehicle taillight comprising a frame configured to be removably mounted to a vehicle, a housing coupled to the frame, a plurality of light emitting diode (LED) positioned along the frame, and a programmable electronic system configured to received an input signal and to selectively provide power to the at least one sets of LED arrays based on a program selected by a user and received input signal. The programmable electronic system is also configured to be selectively placed into a program mode upon activation of a switch, and when in the program mode, to select one of the plurality of programs based on at least one of a turn signal or brake signal of the motor vehicle.

Programmable taillight illumination system

An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.

Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism

A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit. Accordingly, this can significantly reduce the amount of logic duplicated in the decoder units which, in turn, reduces the amount chip area required to support decoding and reduces power consumption. Also, since the decode units are no longer required to support the decoding of such a high number of different instructions, the complexity of each decode unit can be reduced, which can result in increased performance during decode.

Multiple instruction set decoding

A data processing system including multiple execution pipelines each having multiple execution stages E, E, Emay have instructions issued together in parallel despite a data dependency therebetween if it is detected that the result operand value for the older instruction will be generated in an execution stage prior to an execution stage which requires that result operand value as an input operand value to the younger instruction and accordingly cross-forwarding of the operand value is possible between the execution pipelines to resolve the data dependency.

Result bypassing to override a data hazard within a superscalar processor

Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data processing apparatus comprises: decode/issue logic operable to receive and decode an instruction to be processed by the data processing apparatus and to determine when to issue a decoded instructions for execution by execution logic; execution logic operable to execute the decoded instructions; interface logic selectively operable to receive trace information relating to the state of the data processing apparatus generated in response to execution of the decoded instructions for transmission to trace monitoring infrastructure; and throttle logic operable to predict whether issuing the decoded instruction to the execution logic for execution would be likely to cause the trace information to be transmitted to said trace monitoring infrastructure to exceed a capacity of said trace monitoring infrastructure and, if so, to prevent the decode/issue logic from issuing the decoded instruction to the execution logic. Accordingly, the throttle logic reviews each instruction to be executed and predicts whether issuing that instruction at that time will or is likely to cause the capacity to be exceeded. In the event that the throttle logic determines that the capacity is likely to be exceeded, the instruction is prevented from being issued to the execution logic which reduces the likelihood that any state information is lost.

Preventing loss of traced information in a data processing apparatus

Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then be used to correct any decoding which has been performed upon the basis of an assumption that the program instructions are predicated. The predication instruction can predicate a variable number of following instructions. The predication instruction can issue in parallel with an instruction which it predicates and yet the proper identification of the predication instruction need not be confirmed until at least some decoding has been performed upon the other program instruction.

Growing community of inventors

Austin, TX, United States of America

Glen Andrew Harris