International Business Machines Corporation

Glen A Brent

David Bruce Lindquist

Richard I Baum

Donald H Gibson

Casper A Scalzi

Thomas J Dewkett

Harry M Yudenfriend

Balakrishna Raghavendra Iyer

Satya Prakash Sharma

Inderpal Singh Narang

Thomas Edward Cook

Joseph C Elliott

Bhaskar Sinha

Lee Hardy Wilson

Francis E Johnson

Joseph A Williams

Joel Goldman

Roger J Edwards

Gururaj Seshagiri Rao

Hatem Mohamed Ghafir

James J Antognini

Gururaj S Rao

Kenneth R Veraska

Peyton R Williams, Jr

Kushal A Patel

Frank G Bordonaro

Christine R Panner

Hatem M Ghafir

Lee H Wilson

A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as the control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity. Coexecutors can be of the same architecture or of a totally different architecture from the CPs to provide an efficient processing environment for the offloaded functions. The coexecutor interfaces host software which provides the requests to the coexecutor. Offloaded modules, once accessed by the coexecutor, may be cached in coexecutor local storage for use by future requests to allow subsequent invocations to proceed without waiting to again load the same module.

Coexecution processor isolation using an isolation process or having

A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Apparatus for realigning database fields through the use of a crosspoint

Database engine predicate evaluator

Database engine

A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized. functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

A control process which enables a non-supervisory 'using program' (e.g. application programs) to directly interface one or more shared asynchronous hardware facilities in a computer system. Any using program may request the operating system (OS) to set up a 'special environment' with an AHF during which the using program can directly issue requests to the AHF for its services. The OS sets up a session for the using program having the 'special environment', which specifies restrictions on storage accesses by the AHF for accesses made on behalf of the using program--to insure system data integrity. These restrictions are not changeable by the using program. The 'special environment' exists until the session is ended by the using program or by a terminating condition. The 'special environment' is tailored to be different among the different using program concurrently using the same AHF, so that the 'special environment' of one using program cannot interfere with the 'special environment' of another using program. During a session, work requests for any using program are communicated directly to the AHF from the using program, and completion of any work request is communicated directly by the AHF to the using program without any interruption of the using program or OS involvement.

Interface control process between using programs and shared hardware

Provides load balancing, recovery and reconfiguration control for a data move subsystem comprised of a plurality of interconnected and cooperating data move processors (DMPs). Each DMP processor has an associated queue for receiving queue elements (QEs) from central processing units of a data processing system which specify data move requirements of the data processing system. QEs can be transferred between queues of other DMPs or a common queue to achieve load balancing, recovery and reconfiguration control.

Load balancing, error recovery, and reconfiguration control in a data

Virtual addressing is available to a co-processor to asynchronously control the movement of multiple page units of data between different locations in the same or a different media, e.g. main store (MS) and expanded store (ES), or both may be in ES, or both may be in MS. The co-processor controls the asynchronous page movement in parallel with continuing execution of other instructions by the central processor (CP) which requested the page movement. Each page to be moved is specified by an MSB (Move Specification Block). A set of MSBs are addressed by a special type of channel control word (CCW) in a channel program containing one or more CCWs, some of which may address one or more sets of MSBs (one MSB set per CCW) to control the movement of any number of pages. The CPU executes a special ADM SSCH (start subchannel) instruction that passes the page move work to the co-processor to perform the requested page transfer involving one or more sets of MSBs. Flag fields in source and sink specifications in each MSB contains a plurality of flag bits that define: the associated source or sink media, whether the specified address is to be translated as a virtual address or to be handled as an absolute address, whether replication of the source page(s) is to be done at the sink location, and whether the page(s) are to be erased by only accessing the sink pages to control the writing of a predetermined padding character, such as zero, through-out the content of the sink page(s).

Asynchronous co-processor data mover method and means

Logical erasure is done for a virtual page unit of storage in a virtual-page-initialization process (even though the data content of a backing page frame is not physically erased). Pre-initialization controls are associated with each virtual page by a pre-initialization field in each page table entry (PTE). The pre-initialization controls operate differently for fetches and stores within the address translation process. Both fetches and stores test for a pre-initialization state in an F field in the PTE to control if and when any backing page frame can be accessed. While the F field bit is set to its pre-initialization state, no erasure writing is done in any backing page frame for a fetch or full-page store operation. An optional form identifier (form#) field is associated with the pre-initialization state field. The form# field content identifies one of plural form functions or form page frames. Each fetch-only request (occurring prior to a first store to the virtual page) is diverted to a form PF to assure that no prior data in an assigned page frame can be fetched by the user, even though no physical erasure has been done to the contents of any assigned backing page frame. No backing PF needs to be assigned for a fetch-only operation, for which there is no page fault interruption.

Controls for initial diversion of page-frame logical content as part of

Provides a software-to-software interface and a software-to-hardware interface between software users and a hardware ADM facility (ADMF) in a data processing system. Such software user presents only virtual addresses to the software-to-software interface in a MSB list. The user list defines virtual address spaces, including a 'hiperspace', in a manner that represents physical backing media as different random-access electronic storages, such main storage (MS) and expanded storage (ES). The real data transfers are within or between the backing storages. The user list is transformed into an ADM operation block (AOB), which is assigned an ADM UCB in a UCB queue which is associated with an ADM subchannel. The software-to-hardware interface generates an ORB, containing the AOB address, as an operand of a SSCB instruction which is executed to queue the associated subchannel onto one of plural co-processor queues in the ADMF. The ADMF uses the AOB to perform the requested page moves, and generates an interruption upon completion of each request which is sent to the hardware-to-software interface to remove the associated ADMF request from the ADM software request queue and free the associated ADM UCB for use by another user request.

Method and means for enabling virtual addressing control by software

A system and method for merging a plurality of sorted lists using multiple processors having access to a common memory in which N sorted lists which may exceed the capacity of the common memory are merged in a parallel environment. Sorted lists from a storage device are loaded into common memory and are divided into a number of tasks equal to the number of available processors. The records assigned to each task are separately sorted, and used to form a single sorted list. A multi-processing environment takes advantage of its organization during the creation of the tasks, as well as during the actual sorting of the tasks.

Method and apparatus for merging sorted lists in a multiprocessor shared

Database sort and merge apparatus with multiple memory arrays having

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Fishkill, NY, United States of America

Glen A Brent