Applied Materials, Inc.

Giuseppina Conti

Li-Qun Xia

Yan Ye

Thai Cheng Chua

Johanes F Swenberg

Gerardo Delgadino

Xiaoye Zhao

Shreyas Kher

Kang-Lie Chiang

Yuri S Uritsky

Mahmoud Dahimene

Hoiman Raymond Hung

Chikuang Charles Wang

Shankar Muthukrisnan

Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 &#x212b; utilized as a gate dielectric layer in a gate structure.

Method for fabricating an integrated gate dielectric layer for field effect transistors

A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.

Method for modifying dielectric characteristics of dielectric layers

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Oakland, CA, United States of America

Giuseppina Conti