Stmicroelectronics S.r.l.

Giuseppe Visalli

Francesco Pappalardo

Giuseppe Avellone

Agostino Galluzzo

Luca Seghizzi

Mikel Azpeitia Urquia

Francesco Rimi

Linda Montagna

Benedetto Vigna

Chantal Combi

Giuseppe Notarangelo

Marta Mottura

Matteo Fiorito

Disclosed herein is an integrated component formed by a first wafer having first and second trenches defined in a top surface thereof, and a second wafer coupled to the first wafer and formed by a substrate with a structural layer thereon that integrated an electromagnetic radiation detector overlying the second trench. A first cap is coupled to the second wafer, overlies the electromagnetic radiation detector, and serves to define a first air-tight chamber in which the electromagnetic radiation detector is positioned. A stator, a rotor, and a mobile mass are integrated within the substrate and form a drive assembly for driving the mobile mass. The rotor overlies the first trench. A second cap is coupled to the second wafer, overlies the mobile mass, and serving to define a second air-tight chamber in which the mobile mass is positioned.

Method of manufacturing an integrated component with improved spatial occupation, and integrated component

A first wafer of semiconductor material has a surface. A second wafer of semiconductor material includes a substrate and a structural layer on the substrate. The structural layer integrates a detector device for detecting electromagnetic radiation. The structural layer of the second wafer is coupled to the surface of the first wafer. The substrate of the second wafer is shaped to form a stator, a rotor, and a mobile mass of a micromirror. The stator and the rotor form an assembly for capacitively driving the mobile mass.

Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: The processing step comprises the operations of:

Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method

A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives the first address and to transform it into one first cache address; the first cache address is used for accessing the cache memory to retrieve a first part of a tag address portion. The cache controller includes a hit detector establishes an partial hit condition based on a comparison of the retrieved a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer receives the first address and to transform it into one second cache address. The cache controller uses the one second cache address for accessing the cache memory to retrieve a data word in case the partial hit condition is established.

Cache memory system and method with improved mapping flexibility

The method is for estimating the fading coefficients of a plurality of transmission channels on which signals to be sent, generated as a function of a sequence of symbols, are transmitted according to a particular modulation, e.g. AM-PSK modulation. The fading coefficients are estimated by using estimations of the transmitted symbols obtained in advance, thus obtaining DC components of the received signal by coherent demodulation locked to the phases of the transmitted AM-PSK signals, and processing these DC components. The method may not require the choice of a stochastic distribution model of the channel fading, thus it remains efficient even when the channel characteristics vary significantly. Moreover, the method works correctly even if the received stream is disturbed by inter-symbolic interference (ISI) and/or by multi-path fading.

Method of estimating fading coefficients of channels and of receiving symbols and relative single or multi-antenna receiver and transmitter

A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

Method and system for high-speed floating-point operations and related computer program product

Method of estimating fading coefficients of channels and of receiving symbols and related single or multi-antenna receiver and transmitter

Described herein is a method for transmitting data on a bus with minimization of the bus switching activity, comprising the steps of converting the datum to be transmitted from its own original format to a transmission format that minimizes the switching activity on the bus, said conversion consisting in swapping the position of one or more bits of the datum to be transmitted, the swapping being performable according to a plurality of different variants, each of which is identified by a respective sorting pattern, and selecting, between the various sorting patterns, an optimal sorting pattern that minimizes the bus switching activity upon transmission on the bus of the datum generated using said optimal sorting pattern.

Method and device for transmitting data on a single line, in particular for transmitting data on a bus with minimization of the bus switching activity, and corresponding computer product

A method for decoding signals with encoded symbols over a symbol interval that modulate a carrier. The method includes phase locking the signal to be decoded to obtain a phase-locked signal. The value assumed by the phase-locked signal on at least one subinterval in each symbol interval is detected. The method continues with attributing to the decoded symbol corresponding to each symbol interval a value that is a function of the value detected the subinterval. The subinterval in question can be a single subinterval located at the end of the symbol interval. Alternatively, the value assumed by the phase-locked signal on a plurality of subintervals in each symbol interval is detected, and a respective majority value of said phase-locked signal within said plurality of subintervals is identified. A value determined on the basis of the majority value is attributed to the decoded symbol corresponding to each symbol interval.

Method and system for coding/decoding signals and computer program product therefor

In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point teal numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Method and device for floating-point multiplication, and corresponding computer-program product

A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.

Method for transmitting a data flow over an optical bus, corresponding system and computer program product

In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

A data stream (b(t)) including high ('1') and low ('0') logical states is transmitted over an optical link by means of an optical source adapted to be driven via the data strema, to generate an optical signal for transmission over the optical link. The optical signal includes optical pulses generated at the occurrence of high logical states in the data stream b(t). The input data stream b(t) is coded into a coded data stream B(t) prior to the transmission over the optical link. The coding step minimizes the logical high states in the coded data stream, and the optical source is driven by means of the coded data stream wherein the number of logical high states has been minimized.

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Messina, Italy

Giuseppe Visalli