Micron Technology Incorporated

Aptina Imaging Corporation

Giuseppe Rossi

Sandor L Barna

Eric R Fossum

Alf Olsen

Gennadiy A Agranov

Daniel A Van Blerkom

Chiajen Lee

Steve Huang

Roger Panicacci

Kwang-Bo Cho

An analog signal chain for a CMOS active pixel sensor imaging system utilizes, for each amplification stage, a plurality of fixed gain amplifiers instead of a single multi-gain amplifier. The fixed gain amplifier corresponding to the desired gain level is selected and powered on and coupled to the input/output signal paths, while the non-selected fixed gain amplifier(s) are powered off and isolated from the input/output signal paths. Each fixed gain amplifier is operated at a gain bandwidth corresponding to the timing requirements of the imaging system and the gain of the amplifier. Thus, each fixed gain amplifier (other than the one corresponding to the maximum gain of a comparable multi-gain amplifier) operates at a lower level of power consumption than the comparable multi-gain amplifier.

Multi path power for CMOS imagers

Circuits, methods, and systems are disclosed in which a current is provided to compensate for spurious current while receiving signals through a line. For example, the spurious current can be sensed and the compensating current can be approximately equal to the sensed spurious current. The spurious current could include photocurrent from a bright light, and the compensating current can prevent bright light effects.

Providing current to compensate for spurious current while receiving signals through a line

An CMOS active pixel sensor (APS) imaging system include circuitry to compensate for different analog offset levels from the CMOS pixel array. More specifically, the compensation is performed in the analog (charge) domain. A digital correction value, which may be measured as part of the operation or testing of the CMOS APS system, is provided to a offset correction block circuit, to generate an analog electrical signal. The analog electrical signal is supplied to a sample-and-hold circuit including a charge amplifier. The signal read from the pixel array, after conditioning through an analog signal chain, is also supplied to the charge amplifier, which has a linear transfer function and outputs the compensated signal.

CMOS active pixel sensor with a sample and hold circuit having multiple injection capacitors and a fully differential charge mode linear synthesizer with skew control

A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T, and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T

Charge recycling amplifier for a high dynamic range CMOS imager

An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.

Apparatus and method for determining temperature of an active pixel imager and correcting temperature induced variations in an imager

A voltage amplifier is provided. The voltage amplifier includes an amplifier stage to amplify an input signal. A bias current generator supplies a bias current to the amplifier stage. The bias current generator is controllable in response to a frame rate signal that is representative of a video frame rate. A compensation network stabilizes a loop response of the voltage amplifier. The compensation network is controllable in response to the frame rate signal.

Flexy-power amplifier: a new amplifier with built-in power management

A new capacitor architecture includes a front plate of the capacitor formed from a first polysilicon layer. The front plate is surrounded by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first dielectric layer and the second dielectric layer. The two-layer conductive structure is an equal potential structure and includes a conductive coupling between the two layers.

Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor

Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The amplifier can be operated at a low or no power level during an integration period of a photodetector to reduce power dissipation. The amplifier can be distributed, with an amplifier element within each pixel of an array and with amplifier output circuitry outside the pixel array. The amplifier can be a single ended cascode amplifier, a folded cascode amplifier, a differential input telescopic cascode amplifier, or other configuration. The amplifier can be used in pixel configurations where the amplifier is directly connected to the photodetector, or in configurations which use a transfer transistor to couple signal charges to a floating diffusion node with the amplifier being coupled to the floating diffusion node.

Amplification with feedback capacitance for photodetector signals

An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from respective subgroups of sensors, and group select circuits are coupled to outputs from subgroup select circuits associated with respective ones of the groups. A bus is coupled to receive outputs from the group select circuits. A controller can provide control signals to the subgroup select circuits and the group select circuits to selectively enable the respective subgroup select circuits and group select circuits to pass signals from the sensors to the bus one sensor at a time.

Charge mode active pixel sensor read-out circuit

An analog differential voltage circuit is disclosed that enables the combination of a plurality of voltage signals in the analog domain of a CMOS processing system prior to being received by a differential amplifier and prior to being digitized. By programming the column decoder to read out a plurality of column buffer circuits, a plurality of linear operations (e.g., addition, substation, averaging, weighted, sum) may be performed on the plurality of analog voltage levels prior to their being digitized.

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Pasadena, CA, United States of America

Giuseppe Rossi