Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Giuseppe Queirolo

Luca Zanotti

Maurizio Bacchetta

Giovanni Ferroni

Gianfranco Cerofolini

Giampiero Ottaviani

The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. The process forms a polycrystalline silicon film having exceptionally large grains of a size on the same order of magnitude as the dimensions of the patterned details. These exceptionally large grains are obtained by preventing the formation of &ldquo;precursor nuclei&rdquo; of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

Integrated structure comprising a patterned feature substantially of single grain polysilicon

A method for manufacturing a semiconductor device having improved adhesion at an interface between layers of dielectric material, comprising the steps of forming a first layer of dielectric material on at least one part of a structure defined in a semiconductor substrate and forming a second dielectric material layer superimposed on the least one part of the first layer. The method further includes the step of forming, in the part where the first and second layers are superimposed, an intermediate adhesion layer comprising a ternary compound of silicon, oxygen and carbon. The formation of the adhesion layer takes place at low temperature and in an atmosphere kept essentially free of oxidative substances different from those serving to provide the silicon and the carbon to the layer. Preferably the layer is formed by the plasma enhanced chemical vapour deposition technique. The ternary dielectric compound of silicon, oxygen and carbon obtained is preferably useful to aid in adhesion between layers of dielectric materials, particularly in semiconductor devices. Alternatively, in another embodiment of the invention, in a process which is more generally useful for deposition of a dielectric material layer comprising silicon, the layer is formed at low temperature by the chemical vapour deposition technique, preferably plasma enhanced, in an atmosphere kept essentially free of exogenous oxidative substances, (i.e., in which the oxidizer is contained in the molecules used to provide the species of atoms other than oxygen comprised in the layer).

Process for the production of a semiconductor device having better interface adhesion between dielectric layers

A process for cutting a trench in a silicon monocrystal in areas defined by a mask comprises forming a mask that defines an etched area on the surface of a monocrystalline silicon wafer which is eventually covered by a thin layer of oxide. Next, ions are implanted with a kinetic energy and in a dose sufficient to amorphize the silicon down to a predefined depth within the defined area, while maintaining the temperature of the wafer sufficiently low to prevent relaxation of point defects produced in the silicon and to prevent diffusion of the implanted ions in the crystal lattice of the silicon adjacent to the amorphized region. Dislodgment and expulsion of the amorphized portion in correspondence with interface with the adjacent crystal lattice of the silicon is initiated by heating the implanted wafer.

Process for cutting trenches in a single crystal substrate

Process for the production of a semiconductor device having better

Growing community of inventors

Milan, Italy

Giuseppe Queirolo