Infineon Technologies Ag

Intel Corporation

Giuseppe Miccoli

Alfred Vater

Bhaskaran Jayachandran

Friedrich Steffen

Adolf Koller

Jayachandran Bhaskaran

Dicing a semiconductor wafer into chips may include (and structures may result from) forming a lateral chip dicing pattern of vertical metal stack kerf (MSK) structures from a depth below an upper surface of a substrate of a wafer, up through metallization layers of the wafer, to a top surface of the wafer. This dicing pattern may separate or define the perimeters/edges of the chips to be diced. A protective layer over the wafer can be etched to form a pattern of openings to the pattern of MSK structures. Then, a wet etch through the pattern of openings in the protective layer removes the MSK structures and forms lateral chip dicing trench pattern to the depth below the upper surface of the substrate along the intended lateral dicing pattern. A bottom surface of the substrate can be ground to expose the bottom of the trench pattern and dice the chips.

Methods and structures for dicing integrated circuits from a wafer

A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.

Wafer and a method of dicing a wafer

A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface.

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Munich, Germany

Giuseppe Miccoli