Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Giuseppe Meroni

Emilio Giambattista Ghio

Livio Baldi

Danilo Re

Flavio Scarra

Siro M Morganti

The invention relates to a method of automatically shifting from the fabrication of an EPROM cell to the fabrication of a ROM cell, which method is specifically intended for semiconductor electronic circuits having a resident memory and is of the type wherein the structure of at least one memory cell transistor is defined on a semiconductor substrate using photolithographic techniques including an active area and a channel region, the cell being adapted to acquire a logic state selected by the user. Advantageously, the conductivity of the active area is changed to suit the logical contents that the cell is intended to contain.

Method of making a nonvolatile memory cell using EPROM mask and ROM

ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

NOR-type ROM with LDD cells and process of fabrication

Method of making NOR-type ROM with LDD cells

The circuit includes an input register (RI); an output register (RU); an AND plane; and an OR plane. The AND plane has vertical lines (Y), which are controlled by the input register, and horizontal lines (L), which include transistors (TA) arranged in series and controlled by respective vertical lines. The horizontal lines are connected to ground by normally-off transistors (TV) and to the power supply by normally-on transistors (TP). These transistors (TV, TP) are controlled by a first clock signal (CK1.about.). The OR plane has horizontal lines (S) and vertical lines (U). The vertical lines (U) of the OR plane contain normally-off transistors (TO) which are controlled by respective horizontal lines of the OR plane. Horizontal lines of the AND plane and horizontal lines of the OR plane are connected by respective pairs of normally-on transistors (TB) and normally-off transistors (TC) arranged in series between the power supply and ground. In each pair, the normally-on transistor is controlled by a horizontal line of the AND plane, and the normally-off transistor is controlled by a second clock signal (CK2). A horizontal line of the OR plane is connected to the node between the pair. The vertical lines of the OR plane are connected to the power supply by respective transistors (TR), which are controlled by a third clock signal (CK2.about.), and to the output register by pass transistors (P), which are controlled by a fourth clock signal (CK3.about.).

Monostabilized dynamic programmable logic array in CMOS technology

Growing community of inventors

Agrate Brianza, Italy

Giuseppe Meroni