Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (grenoble) Sas

Giuseppe Maruccia

Riccardo Locatelli

Marcello Coppola

Lorenzo Pieralisi

Giuseppe Guarnaccia

Michael Soulie

Raffaele Guarrasi

Valerio Catalano

Hajer Ferjani

Philippe Teninge

A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

Method and apparatus for supporting the use of interleaved memory regions

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

Method and apparatus for use with different memory maps

A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.

Method for transferring data from a source target to a destination target, and corresponding network interface

This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: The control data and the actual data to be transferred are stored in separate first and second memory means.

Buffering architecture for packet injection and extraction in on-chip networks

A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.

System for transmitting data between transmitter and receiver modules on a channel provided with a flow control link

A bandwidth allocator to allocate in real time shared resources of a network on-chip is disclosed. The bandwidth allocator routes data packets between elements of the network in response to requests to access the shared resources. The bandwidth allocator could include a plurality of network interfaces to process the data packets to be routed within the network and a plurality of routers for routing the data packets through the network. A processor, distributed within the routers, controls the routers and the transmission of each data of the data packets through the routers to provide a bandwidth for each data flow. The network interfaces is adapted to fill a header field of each data packet with header field information depending on a requested bandwidth. The processor controls the transmission of the data packets through the routers as a function of the value of the header field information of each data packet.

On-chip bandwidth allocator

A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure. Processing circuitry is distributed within the N routers and the N network interfaces for determining direction of the data packet to be transmitted over a path from a source element to a destination element in the ring structure, and for determining at each router in the path which virtual channel is to be used to avoid deadlocks in the transmission.

Growing community of inventors

Grenoble, France

Giuseppe Maruccia