International Business Machines Corporation

Giuseppe La Rosa

Ping-Chuan Wang

Jack Allan Mandelman

Kevin W Kolvenbach

Rama Divakaruni

Fernando Jose Guarin

Stewart E Rauch, Iii

Carl John Radens

Louis L Hsu

Oleg Gluschenkov

Herbert Lei Ho

Thomas W Dyer

Jochen C Beintner

Wen Liu

Alvin Wayne Strong

Stephen Dale Wyatt

Rajesh Rengarajan

You Li

Yujun Li

John Greg Massey

Mary Elizabeth Weybright

Joseph M Lukaitis

Radhika Srinivasan

Paul A Hyde

Kai Xiu

Anastasios A Katsetos

Stephen P Boffoli

B B (Bob) Lawhorn

Ryota Katsumata

Electrostatic discharge protection circuits and methods for protecting a core circuit from an electrostatic discharge event. The protection circuit may include a first anti-parallel diode pair including a first terminal coupled to an input/output pad, and a second anti-parallel diode pair including a second terminal coupled to a negative power supply voltage. The second anti-parallel diode pair is coupled in series with the first anti-parallel diode pair at a node. An offset pad is coupled to the node. The offset pad is configured to receive a first signal that is a duplicate of a second signal that is received at the input/output pad.

Electrostatic discharge protection solutions

A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (&#x394;T value) is determined for the given device based on the poly-gate temperature and the channel temperature. A device comprises a heating device having a poly gate with at least one contact at each end thereof and a plurality of monitor device spaced at known distances from the heating device

Structure and methodology for characterizing device self-heating

A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.

Method and apparatus for dynamic characterization of reliability wearout mechanisms

A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.

Structure and method for thermally stressing or testing a semiconductor device

A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.

Trench capacitor vertical structure

A recovery circuit and a method for employing the same are provided. The recovery circuit has a current driver and, preferably two pass-gates, a first pass-gate connected in series to the current driver and a second pass-gate connected to a ground. The recovery circuit also has a recovery assembly or element and one or more contacts operatively connecting the recovery circuit to a wearout sensitive circuit or circuit element.

Method and circuit for element wearout recovery

P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

PMOSFET device with localized nitrogen sidewall implantation

A process for in-line testing of a metal-oxide-semiconductor field effect transistor (MOSFET) device for negative bias thermal instability (NBTI), which degrades the gate oxide of the MOSFET device. The process generally comprises four steps. First, a hole injection method is selected that produces approximately the same gate oxide degradation as the NBTI under test. Second, a correlation is established between the NBTI degradation and device shifts due to the selected hole injection degradation method. Third, an in-line procedure is developed based on the hole injection method, using the second step to relate the measured shift to NBTI. Finally, a NBTI specification is defined based on the hole injection method using the second step. The MOSFET device is preferably a p-type MOSFET device and the hole injection method is preferably a channel hot-carrier stress method.

Line monitoring of negative bias temperature instabilities by hole injection methods

A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Method and device for array threshold voltage control by trapped charge in trench isolation

A method and structure for disconnecting shorted bitlines from a dynamic random access memory circuit includes supplying a precharge voltage to equalization lines in the integrated circuit, supplying a negative voltage to wordlines in the integrated circuit, activating equalization devices connected to the bitlines and the equalization lines and maintaining the precharge voltage and the negative voltage until a short between one of the bitlines and one of the wordlines causes a corresponding equalization device of the equalization devices to have a permanently elevated threshold voltage.

Auto-programmable current limiter to control current leakage due to

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Fishkill, NY, United States of America

Giuseppe La Rosa