Stmicroelectronics S.r.l.

Giuseppe Greco

Fabrizio Roccaforte

Ferdinando Iucolano

Simone Rascuna′

Tonio Gaetano Biondi

Andrea Severino

Gaetano Bazzano

Salvatore Rinaudo

Filippo Giannazzo

Simone Rascunà

A manufacturing process forms an HEMT device. For the manufacturing process includes forming, from a wafer of silicon carbide having a surface, an epitaxial layer of silicon carbide on the surface of the wafer A semiconductive heterostructure is formed on the epitaxial layer, and the wafer of silicon carbide is removed.

HEMT device having low conduction losses and manufacturing process thereof

Merged-PiN-Schottky, MPS, device comprising: a solid body having a first electrical conductivity; an implanted region extending into the solid body facing a front side of the solid body, having a second electrical conductivity opposite to the first electrical conductivity; and a semiconductor layer extending on the front side, of a material which is a transition metal dichalcogenide, TMD. A first region of the semiconductor layer has the second electrical conductivity and extends in electrical contact with the implanted region, and a second region of the semiconductor layer has the first electrical conductivity and extends adjacent to the first region and in electrical contact with a respective surface portion of the front side having the first electrical conductivity.

Contextual formation of a junction barrier diode and a Schottky diode in a MPS device based on silicon carbide, and MPS device

A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant ('lattice mismatch'), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof

An embodiment of a design of one or more devices such as e.g. integrated circuits is ported from a source design technology to a target design technology by: &#x2014;producing a standardized set of porting rules which translate device information related to the device or devices from the source design technology to the target design technology, and&#x2014;creating a migrated design for the device or devices resulting from porting the CAD design from the source design technology to the target design technology by applying the standardized set of rules to the device information related.

Method for technology porting of CAD designs, and computer program product therefor

A method models the electrical characteristics of wide-channel transistors, such as power transistors, by generating a lumped-element distributed circuit model. More specifically, the active area of the transistor is organized in elementary transistor cells, which are substituted by active lumped elements. Similarly the passive area of the transistor is organized in elementary strip-lines, which are substituted by passive lumped elements. Preferably, the parameters of the lumped elements are extracted automatically from layout information, such as path dimensions, and technological data, such as sheet resistance of the metal layers, sheet resistance of the polysilicon layers and oxide thickness.

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Misterbianco, Italy

Giuseppe Greco