Stmicroelectronics S.r.l.

Giuseppe Gramegna

Alessandro D'Aquila

Benedetto Marco Marletta

Michele Vaiana

Antonio Magazzu

Antonio Magazzu'

Antonio Magazz'

B Marco Marletta

Precision and reliability of a current limited mode output power control of an RF amplifier is enhanced by sensing the base current of the current controlled output power transistor. The base current is compared to a control current that is normalized by scaling it as a function of the current gain of a bipolar junction transistor of similar characteristics as the output power transistor. Fabrication process spread of current gain figures of bipolar junction transistors is effectively compensated. Moreover, by using a band-gap temperature compensation control current that is eventually &#x3b2;-scaled before comparing it with the sensed base current of the output power transistor, the output power may be effectively controlled and maintained constant over temperature as well as process spread variations.

Output power control of an RF amplifier

A device calibrates the frequency of an oscillator. The oscillator has first and second inputs and generates an output frequency responsive to a first voltage signal at the first input. The calibration device generates a calibration signal applied at the second input of the oscillator for calibrating its output frequency and comprises a counter. The counter has a first input frequency proportional to a reference frequency and a second input frequency proportional to the output frequency. The counter counts the time window number given by the ratio of the second to first frequencies. The device comprises a comparator that compares the counted time window number with a prefixed time window number. The calibration device changes the value of the calibration signal if the counted time window number is different from the prefixed time window number and until the counted time window number is equal to the prefixed time window number.

Device for calibrating the frequency of an oscillator, phase looked loop circuit comprising said calibration device and related frequency calibration method

A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Method and circuit for minimizing glitches in phase-locked loops

A high-precision biasing circuit is provided for a CMOS cascode stage with inductive load and degeneration. The cascode stage includes at least two MOS transistors serially connected between a first voltage reference and a second voltage reference. The biasing circuit includes at least a first MOS replica transistor and a second MOS replica transistor, and two current generators for biasing the first and second MOS replica transistors. A circuit block detects a voltage value on a terminal of the second replica MOS transistor and applies a voltage to a gate terminal of the first replica transistor. Two circuit block implementations include a voltage amplifier and a folded cascode amplifier closed in a shunt feedback. Both implementations allow the threshold voltages of the cascode stage transistors to be tracked, as well as their Early and body effects.

High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers

A low noise adaptive bias circuit is provided for a low noise bipolar junction input transistor having an emitter degeneration inductance, of an integrated high frequency functional circuit driven by the collector current of the input transistor. The bias circuit includes a shunt line connecting the base node of the input transistor to a first supply node of opposite sign of that of a second supply node to which is coupled, through the degeneration inductance, to the emitter of the input transistor. The shunt line includes a bias current generator dependent, in an inversely proportional manner, on the current gain of the input transistor, and a resistance dependent, in a directly proportional manner, on the current gain of the input transistor.

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Catania, Italy

Giuseppe Gramegna