Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Giuseppe Giandonato

Silvano Giorcelli

Vinicio Vercellone

Roberto Montagna

Carlo Demichelis

Riccardo Melen

Enrico Impallomeni

Giorgio Sofi

Giorgio Martinengo

Sergio Villone

Valerio Barcaroli

Riccardo Cedolin

Francesco Gandini

Wolmer Chiarottino

Gian P Balboni

The switching element for self-routing multistage packet-switching interconnection networks comprises: an input unit, composed of as many sections (IMA, IMB) as the element inputs are, each section comprising a FIFO memory (FIFA, FIFB) for packet buffering; a switch (SW) associated with a control unit (SCU) which, for each packet to be forwarded, sets up the connection requested for that packet between one input and one or more outputs of the element (ECP), on the ground of a routing tag associated with each packet and comprising a first and a second portion relative to normal routing and to broadcasting in the different stages of the network (RC), and solves possible routing conflicts between packets simultaneously arriving at different inputs; and an output unit, composed of as many sections (RU0, RU1) as the element outputs are and performing the whole of the functions necessary for the correct packet forwarding towards a destination. The control unit (SCU) of the switch (SW) is arranged to handle broadcasting of a packet independently of all other elements (EDP) in the same stage, so as to allow broadcasting also to a number of destinations different from a power of 2 (for an element with two inputs and two outputs) and cooperates with the memory (FIF) storing the packet to be broadcast in such a way that broadcasting does not give rise to internal blocking in the network (RC). Said control unit (SCU) moreover solves routing conflicts so as to set an upper bound to packet permanence time within the network (FIG. 2).

Switching element for self-routing multistage packet-switching

A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.

Modular signal-processing system

An apparatus for handling incoming signals from sensors monitoring the state of certain points of a telephone circuit as well as outgoing signals for drivers associated with other circuit points includes a preprocessor PE inserted between the assembly DR of sensors and drivers, on the one hand, and a processor EL, on the other hand. The preprocessor and the processor have access, through a bus 5, to a common memory ME having areas allocated to the scanning of the circuit points, to time-counting operations and to the storage of messages from the preprocessor. A microprogram memory in the preprocessor, when addressed by a sequencer CM started automatically, manually or in response to an instruction from the processor, initiates a temporary seizure of the bus--if the latter is available--whereupon an initial address is delivered from the common memory ME to a working memory ML in the preprocessor to start the scanning of successive pairs of circuit points. If the pair being scanned is connected to sensors, a change of state in either point is reported to the processor if verified by an integration procedure under the control of a read-only memory MIN in the preprocessor; if the points are connected to drivers, the same read-only memory MIN controls the emission of outgoing signals to them. Upon the completion of the scanning operation, the preprocessor performs lower-priority tasks of generating clock messages and measuring signal durations before relinquishing control of the bus.

Device for processing telephone signals, including a processor and a

At a subscriber station AU communicating with a central office of a data network, a logic unit UM includes a processing subunit UE which, under the control of a microprogrammed subunit UC comprising a microinstruction memory MM and a sequencer SQ, digitally demodulates an incoming carrier and synthesizes an outgoing carrier modulated in the DPSK (differential-phase-shift keying) mode. The modulation is effected by multiplying stored bits of an outgoing signal, read out from a data memory MD, with bits representing digitized sine and cosine samples of the carrier wave obtained from a calculator AL within subunit UE, followed by conversion to analog form and filtering; demodulation is carried out in a similar manner, after conversion of analog samples of the incoming carrier to digital form, by multiplying the resulting bits with those of the calculated sine and cosine samples. The sampling instants are established by a timing signal T2 digitally synchronized with the central-office clock through a phase-locking loop including an adjustable frequency divider DP controlled by an error signal from the calculator AL, emitted when the peak-indicating derivative sample has an absolute value exceeding a predetermined threshold.

Terminal equipment for data-transmission network including digitally

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Turin, Italy

Giuseppe Giandonato