Stmicroelectronics S.r.l.

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (rousset) Sas

Giuseppe Falconeri

Daniele Mangano

Salvatore Pisasale

Mirko Dondini

Alberto Scandurra

Salvatore Marco Rosselli

Giovanni Strano

Francesco Giotta

Ignazio Antonino Urzi′

Ignazio Antonino Urzi'

Giovanni Strani

A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.

Communication system for interfacing a plurality of transmission circuits with an interconnection network, and corresponding integrated circuit

In a method for making an on-chip interconnect for conveying between a set of initiators and a set of targets in which traffic is organized in classes of service, priority values representing the classes of service are associated with the traffic. The method further includes propagating the priority values towards the points of the network where an arbitration is performed between two classes of service of the traffic, and providing arbitration as a function of the priority values.

On-chip interconnect method, system and corresponding computer program product

A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.

Buffer for ordering out-of-order data, and corresponding integrated circuit and method for managing a buffer

A communication system transmits data from a first circuit over a communication channel to a second circuit, the data having a first priority and a second priority. The communication system includes a separation circuit, a first-in first-out (FIFO) memory, and a control circuit.

Communication system and corresponding integrated circuit and method

A system such as a 'System-on-Chip' includes an interconnection network, a set of initiator modules for transmitting data towards the interconnection network and at least one communication arbiter for deciding, as a function of a set of configuration values, which transmissions of the initiator modules have access to the interconnection network. At least one configuration value is associated with each initiator module. A control device coupled to at least one of the initiator modules detects a communication status associated with the transmissions of the coupled initiator and generates a communication status signal whose value is representative of such status, determines a filtered value representative of a series of the values of the communication status signal, and selectively varies one of the configuration values as a function of the filtered value.

Control device for a system-on-chip and corresponding method

An interface device, such as for a System-on-Chip (SoC) bus, transfers data from an input queue through an output to a target. The interface device includes a buffer network for buffering input data when the target is not available for receiving the data. A multiplexer switches between a first operating condition for directing to the target the data from the input queue, and a second operating condition for directing to the target the buffered data from the buffer network. A finite-state machine selectively switches the multiplexer between the first operating condition and the second operating condition based on an acknowledgement signal received from the target. This indicates the availability of the target for receiving the data.

Interfacing device and method, for example for systems-on-chip

A method of performing transactions in a communication network in which is exchanged between Intellectual Property (IP) cores has information transported in packets which include a header for transporting control information and one or more payloads transporting content. A versatile packet format is used which is adapted to transport different traffic patterns generated by the IP cores using different protocols for simple interoperability between the IP cores and also providing configurability of the granularity arbitration process to correct crossing the routers in the communication network.

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Sant'Agata Li Battiati, Italy

Giuseppe Falconeri