Alcatel Lucent

Italtel S.p.a.

Politecnico Di Milano

Giuseppe De Blasio

Luca Salgarelli

Arnaldo Spalvieri

Giorgio Barzaghi

Marzio Gerosa

Riccardo Gemelli

Marco Pavesi

Andrea Galbiati

Giacomo Mirelli

Francesco Gringoli

Thomas Blondel

Paolo Di Prisco

Giuliano Corbetta

Dalmazio Mandich

Francesco Vodola

Marco Pasotti

Giuseppe Luigi Mandelli

Gianluca Boiocchi

Mario GL Frecassetti

Emanuele Antonio Pascale

It is disclosed a method for routing an upstream traffic flow generated at a node of a radio access network. The method comprises the following steps: a) at the node, splitting the upstream traffic flow in packets; b) at the node, inserting in at least one of the packets an information indicative of the destination of the upstream traffic flow; and c) routing the at least one of the packets according to the information indicative of the destination through a packet-switch operation.

Method for routing a traffic flow in a radio access network and node for implementing such a method

A method of transmitting packets wherein said packets are comprised in a plurality of flows, the flows comprising flow characteristics controlling admission of incoming flows. A plurality of admitted incoming flows with the same class of service are inserted into a queue. A committed information rate value corresponding to said queue and a bandwidth available for transmission of said queue according to the identified committed information rate value are identified. An order for transmission for the queues is established based on the class of service of the queue and the identified bandwidth. A plurality of cells of the same size are generated from a plurality of frames and the cells are distributed between a plurality of individual transmission channels according to the ordered defined for transmission. A transmitter equipment and a receiver equipment are also disclosed.

System and method for multi-channel packet transmission

For transmitting packets over radio communication links wherein flows of packets are delivered containing protected packets and unprotected packets, the status of propagation of the packets is verified in order to detect the presence of a faulty condition. If no faulty condition is detected, protected packet are transmitted over a first radio link wherein the transmission occupies a first portion of available bandwidth on the first radio link, and unprotected packets are transmitted on at least part of the remainder of the available bandwidth of the first radio link and at least part of available bandwidth the second radio link. If a faulty condition is detected, a protected packet is transmitted over the first radio link wherein the transmission occupies a first portion of available bandwidth on the first radio link, a duplicate of the protected packet is transmitted over the second radio link wherein said transmission occupies a second portion of available bandwidth on the second radio link, and unprotected packets are transmitted on at least part of the remainder of the available bandwidth of the first radio link and at least part of the remainder of the available bandwidth of the second radio link.

System and method for selective protection switching

A method of radio transmitting packets and transmitter. The packets are identified by at least one respective transmission criterion which is selected from either one or a combination of the following criteria:

Selective radio transmission of packets

It is disclosed a method for implementing a circuit emulation service through a packet-switched network, wherein the packet-switched network cooperates with a first interface and a second interface suitable to connect a first user and a second user, respectively, to the packet-switched network. The method comprises: a) at the first interface, receiving a TDM flow from the first user; b) converting the TDM flow in packets formatted according to the circuit emulation service, wherein at least one of the packets comprises a header in turn comprising a redundant field; c) compressing the header into a compressed header by processing the redundant field, and forming a compressed packet comprising the compressed header; d) transmitting the compressed packet through the packet-switched network to the second interface.

Circuit emulation service method and telecommunication system for implementing the method

A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding

A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, or FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through as multiple point-to-point buses to transfer signals two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol

Growing community of inventors

Rome, Italy

Giuseppe De Blasio