Stmicroelectronics S.r.l.

Freescale Semiconductor,inc.

Stmicroelectronics (grenoble 2) Sas

Giuseppe D'Angelo

Giovanni Moselli

Virginia Clemente

Stefano Baratto

Michele Bisogno

Andre Roger

Mario Lavorgna

Leos Chalupa

Antonio Anastasio

Umberto Macri

Francesco Giuffré

Vincenzo Buccino

Carolina Verde

Fabio Marchio′

A method for controlling a BLDC motor includes controlling the rotational speed or position of the BLDC motor based on a position of the rotor of the motor. The BLDC motor is driven by a three-phase inverter. A PWM signal is generated for three PWM phases, each including a pair of complementary signals with dead-time and having a duty cycle based on the current position of the rotor. The complementary signals are supplied to a respective high side and low side switch of each of three arms of the three-phase inverter, and a zero-crossing time measurement is performed on each of the back electromotive forces. Corresponding signals are obtained indicating the zero-crossing times. Trigger signals are generated, and the occurrence of a time interval corresponding to the dead time in the respective PWM phase is identified. The zero-crossing time measurement is performed during the occurrence of the dead-time.

Method for controlling a BLDC motor and corresponding control circuit

In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.

Analog-to-digital converter circuit, corresponding device and method

A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

High resolution time capture circuit and corresponding device, capture method and computer program product

A half-bridge driver circuit includes an amplifier configured to generate a measurement signal indicative of a current flowing through a shunt resistor. A processing circuit is configured to selectively acquire a sample of the measurement signal in response to a trigger signal. A synchronization circuit is configured to determine a first value indicative of the switch-on duration of a high side control signal, determine a second value indicative of the switching period of the high side control signal, compute a third value based on the first and second values, generate a third signal based on the third value when the next switching period of the high side control signal starts, start a second counter in response to the third signal, compare the count value of the second counter with a reference value to generate a fourth signal, and generate the trigger signal as a function of the fourth signal.

Half-bridge driver circuit, related integrated circuit and system

Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Fault detection circuit for a PWM driver, related system and integrated circuit

A half-bridge driver circuit is configured to generate drive signals based on control signals. A processing circuit is configured to generate high side and low side control signals based on a control signal. An edge detector is configured to generate first and second signals in response to rising and falling edges in the control signal. A state machine transitions between states in response to the first and second signals, and is configured to sequentially, in response to the first signal, set the high side and low side control signals low; in response to the second signal, set the high side control signal high and the low side control signal low; in response to the first signal, set the high side and low side control signals low; and in response to the second signal, set the high side control signal low and the low side control signal high.

An electric motor is controlled by means of pulse-width modulated control signal having edge transitions occurring at certain transition count values of the pulses of a clock signal which is frequency-modulated with a step-wise frequency modulation (e.g., SSCG or Spread Spectrum Clock Generation). A frequency unmodulated clock signal is provided having a fixed period indicative of the period of the pulse-width modulated control signals. The transition count values are set as a function of a predicted count value and/or a predicted frequency value for the frequency-modulated clock signal. Prediction occurs as a function of the frequency unmodulated clock signal, so that the transition count values are compensated against the step-wise (e.g., SSCG) frequency modulation.

Method of controlling electric motors, corresponding system, electric motor and computer program product

A driver device for driving a DC motor using PWM modulated drive signals includes comparator circuits for producing digitalized Back-EMF signals having first and second values as a function of the Back-EMF signals being above or below a respective threshold, and an inverter for driving the PWM modulated drive signals in a phased relationship with the digitalized Back-EMF signals. The driver device also includes controller circuits configured for controlling the respective threshold by minimizing the error between a time measured between two consecutive opposed edges of the digitalized Back-EMF signal and half a time measured between two consecutive homologous edges of the digitalized Back-EMF signal.

Method of driving brushless motors, corresponding device, motor and computer program product

Electric circuit for estimating the angular position of a rotor of an electric motor, including: a sensing module configured to receive at least one electric signal representative of a drive current of the electric motor and to generate a measurement signal indicative of a switching of the at least one electric signal and a switching index indicative of the type of switching, rising or falling, of the at least one electric signal; and a computing module configured to supply, from the measurement signal and switching index a position signal representative of an angular position of the electric motor rotor.

Electric circuit and method for estimating the angular position of a rotor of an electric motor, and device for controlling an electric motor

An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities. The calculation of the square root includes: calculating an approximated value of the square root, having a first precision, and then calculating a corrective value and combining said approximated value with said corrective value to obtain a square root value having a second precision greater than the first precision.

Method and system for controlling electrical machines

A control circuit controls an electric motor and includes: a measuring device configured to measure a first phase current of the motor and provide a corresponding first analog signal; an analog-to-digital converter structured to convert the first analog signal into a first digital signal; a conversion module for generating a first converted digital signal representative of the first digital signal expressed in a rotating reference system; a node structured to compare the first converted digital signal into a first reference signal and generate a first error signal; and a measure control circuit structured to provide a timing signal of the analog-to-digital converter depending on the first error signal and a time delay introduced by the measuring device.

Control circuit of an electric motor with a measure delay compensation and motor system comprising the circuit

A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm.

Processor system employing a signal acquisition managing device and signal acquisition managing device

A method for estimating values assumed at a certain instant of each period by currents flowing respectively in two distinct windings of a poly-phase load controlled in a space vector modulation (SVM) mode, using a same measuring device, may include coupling the measuring device to the first winding and measuring a current flowing therethrough with an anticipation from the certain instant smaller than or equal to an SVM half-period. The method may also include coupling the measuring device to the second winding, measuring a current flowing therethrough at the certain instant, coupling the measuring device to the first winding, and measuring a current flowing therethrough with a delay equal to the anticipation. The method may also include estimating a value assumed at the certain instant by the current flowing through the first winding based upon the two measured values with the anticipation and with the delay respectively.

Method and related device for estimating two currents flowing simultaneously through respective windings of a poly-phase electrical load driven in SVM mode

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Tufino, Italy

Giuseppe D'Angelo