Stmicroelectronics S.r.l.

Giuseppe Croce

Alessandro Moscatelli

Pietro Montanini

Marta Mottura

Paola Galbiati

Andrea Paleari

Alessandra Merlini

A MOS transistor includes a semiconductor layer with a drain region and a body region. A first insulating layer is disposed over the semiconductor layer, a gate-precursor layer is disposed over the first insulating layer, a second insulating layer disposed over the first insulating layer and a third insulating layer disposed over the second insulating layer. A source opening extends through the third insulating layer, the second insulating layer, the gate-precursor layer, and the first insulating layer. An implant through the source opening forms a source-precursor region in the semiconductor layer. The source opening is then lined and an body contact opening is made through the liner, the source-precursor region and into the body region. An implant through the body contact opening forms the body contact region below the source-precursor. The body contact opening is then filled with a metal.

Method for manufacturing a transistor with self-aligned terminal contacts

An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Deep contacts of integrated electronic devices based on regions implanted through trenches

A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Method for manufacturing a MOS transistor

MOS transistor

A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Metal oxide semiconductor field-effect transistor having a gate oxide layer with portions of different thicknesses and associated methods

An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

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Villasanta, Italy

Giuseppe Croce