Stmicroelectronics S.r.l.

Giuseppe Castagna

Maurizio Francesco Perroni

Fabio Enrico Carlo Disegni

Salvatore Polizzi

Vincenzo Matranga

Salvatore Mazzara

MaurizioFrancesco Perroni

Guido Desandre

Salvatore Imbesi

A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.

Memory device with internal measurement of functional parameters

A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.

Circuit and method for biasing nonvolatile memory cells

An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.

Negative voltage management module for an address decoder circuit of a non-volatile memory device

A current-generator circuit is for generation of an output current of a value that is configurable as a function of a configuration signal. The circuit may have a first reference resistor element traversed by an intermediate current, the value of which is a function of a reference current, for supplying a first reference voltage. The circuit may also include a resistive divider stage receiving the configuration signal and supplying a second reference voltage as a function of the first reference voltage and of the configuration signal. A second reference resistor element supplies, as a function of the second reference voltage (V), the output current on the output terminal. The value of resistance of the second reference resistor element may be matched to a respective value of resistance of the first reference resistor element.

Circuit for generation of an electric current with a configurable value

A nonvolatile memory device includes a discharge circuit configured to selectively connect circuit nodes to discharge terminals through corresponding discharge paths, and an accumulation device for accumulating electric charge. A driving circuit is for driving the discharge circuit in such a way to connect at least a part of such circuit nodes to the discharge terminals if the value of the external supply voltage falls below a corresponding threshold. A supply circuit is for supplying the driving circuit with an intermediate supply voltage. Each one of the intermediate supply voltages is the corresponding external supply voltage when the value of the external supply voltage is higher than the corresponding threshold, or it is an internal voltage locally generated by the supply circuit by exploiting the electric charge stored by the accumulation device when the value of the external supply voltage is lower than the corresponding threshold.

Control system for memory device

A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal.

Row decoder circuit for a phase change non-volatile memory device

A circuit for reading memory cells includes: a sense node connectable to a memory cell; a sense device connected to the sense node and configured to be activated in a precharging step which precedes a cell reading step and to provide such an output signal to assume logic values dependent on an electric signal present at the sense node; a precharging circuit connected to the sense node and configured to be activated to make the sense node reach a precharging voltage and to be deactivated upon the output signal switching in the precharging step.

Circuit for reading non-volatile memory cells having a precharging circuit activated after the activation of a sense circuit

An address decoding device may include a supply terminal for a supply voltage, a conductive path configured to provide an electric signal, associated with an address of at least one memory cell, and an address terminal connected to the conductive path and structured to receive the electric signal. An address decoder may be connected to the address terminal to receive the electric signal. The decoder may have a decoding operative voltage associated therewith. A switch circuit may be structured to electrically connect the address terminal to the supply terminal when the address terminal takes a threshold voltage imposed by the electric signal, and may bring the address terminal to the decoding operative voltage.

Address decoding device

An electrically programmable non-volatile memory device being integrated on a chip of semiconductor material is proposed. The memory device includes a plurality of sectors of memory cells each one being formed in a respective well of the chip; each sector includes a plurality word lines each one for accessing a corresponding block of memory cells of the sector; the memory device includes a first biasing line of the wells and a second biasing line of the word lines, biasing circuitry for providing a first bias voltage to the first biasing line and a second bias voltage to the second biasing line, selection circuitry for selectively connecting the first biasing line to the well of at least one selected sector and for selectively connecting the second biasing line to at least one selected word line of each selected sector, first charge transfer circuitry for bringing the first biasing line from the first bias voltage to a target voltage according to a pilot transient trend, the target voltage being between the first bias voltage and the second bias voltage, second charge transfer circuitry for bringing the second biasing line from the second bias voltage to the target voltage. The second charge transfer circuitry includes circuitry for binding the second biasing line to bring itself from the second bias voltage to the target voltage according to a transient trend being scaled with respect to the pilot transient trend.

Non-volatile memory device with controlled discharge

An electrically programmable non-volatile memory device includes a plurality of memory cells, a plurality of lines for selectively biasing the memory cells, reconnection circuitry for reconnecting a pair of selected lines having different voltages, and a controller for controlling the memory device. The reconnection means includes a discharge circuit for discharging one of the selected lines being at the higher voltage in absolute value, an equalization circuit for equalizing the selected lines, a comparator circuit for measuring an indication of a voltage difference between the selected lines, and an evaluation circuit responsive to an enabling signal from the controller for activating the discharge circuit until an absolute value of the voltage difference exceeds a threshold value and for disabling the discharge circuit and enabling the equalization circuit when the absolute value of the voltage difference reaches the threshold value.

Non-volatile memory device with reconnection circuit

A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding transistor of the buffer stage. Each portion may include a final stage with a complementary pair of MOS transistors inserted between two supply voltage references, and a third MOS transistor having its conduction terminals connected between one of the voltage references and an interconnection node of the complementary pair and receiving, on its control terminal, an activation pulse signal coming from a logic network incorporating at least one delay chain.

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Palermo, Italy

Giuseppe Castagna