Micron Technology Incorporated

Giuseppe Cariello

Jonathan Scott Parry

Fulvio Rori

Reshmi Basu

Deping He

Chiara Cerafogli

David Aaron Palmer

Luca Porzio

Scott Anthony Stoller

Jonathan W Oh

Harish Reddy Singidi

Preston Allen Thomson

Devin M Batutis

Roberto Izzi

Nitul Gohain

Jung Sheng Hoei

Qing Liang

Ugo Russo

Mauro Luigi Sali

Jameer Mulani

Marco Domenico Tiburzi

Justin Bates

Stefano Falduti

Kishore Kumar Muchherla

Stephen D Hanna

Christian M Gyllenskog

Pitamber Shukla

Antonino Pollio

Carmine Miccoli

Jeffrey Scott McNeil, Jr

Patrick Miesen

Ryan Hrinya

Gaspare Giglio

Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

Suspending operations of a memory system

Methods, systems, and devices for wear leveling techniques using data characteristics are described. The described techniques provide for wear leveling across blocks of a memory system. A controller of the memory system may include additional criteria for determining a destination block for an operation, which may include a characteristic of data associated with the operation. The controller may select a destination block according to both an age of the block and the characteristic of the data. For example, the controller may select a relatively young block for data having a first characteristic and may select a relatively old block for data having a second characteristic. In some cases, the controller may partition free blocks into sub-pools based on an average age of virtual blocks (VBs) associated with each free block.

Wear leveling techniques using data characteristics

Methods, systems, and devices for improved efficiency for consecutive read operations are described. For example, a memory system may receive a first command indicating a first read operation in a block of memory cells that are each configured to store more than one bit. In response to receiving the first command, the memory system may initiate the performance of the first read operation by applying a voltage to a set of access lines associated with the block of memory cells. The memory system may additionally receive a second read command indicating a second, consecutive read operation in the block of memory cells, where the second command includes an indication to refrain from discharging the set of access lines. Here, the memory system may initiate the performance of the second read operation without first discharging the set of access lines after the performance of the first read operation.

Efficiency for consecutive read operations

Methods, systems, and devices for sacrificial block pool are described. For instance, a memory device may allocate a first pool of blocks and a second pool of blocks. The first pool of blocks may be associated with access operations in which each memory cell stores a single bit and the second pool of blocks may be associated with operations where each memory cell stores a single bit or multiple bits. The memory device may perform access operations according to the allocation, where for the access operations a first wear-leveling criteria is applied to a first subset of the second pool of blocks and a second wear-leveling criteria is applied to a second subset of the second pool of blocks. The memory device may move a block of the second subset to the first pool of blocks based on an amount of access operations associated with the block satisfying a threshold.

Sacrificial block pool

Methods, systems, and devices for multi-level cell maintenance operations are described. A controller of a memory device may perform a two-portion maintenance operation in order to transfer data from a first block of memory cells to a second block of memory cells. For example, during a first portion of the maintenance operation, the controller may read first data from the first block of memory cells and perform a first error control operation to correct the first data. The controller may store second data associated with the first error control operation to volatile memory of the memory device in response to performing the first error control operation. During a second portion of the maintenance operation, the controller may perform a second error control operation using the second data associated with the first error control operations stored to the volatile memory of the memory device.

Multi-level cell maintenance operations

Methods, systems, and devices for techniques for sequential access operations are described. In some cases, a memory system may be configured to suppress storing a checkpoint while in a sequential write mode. While in the sequential write mode, the memory system may initiate and store a first a checkpoint, along with an indication that the checkpoint was stored as part of the sequential write mode. Subsequently, the memory system may initiate a second checkpoint and suppress storing the second checkpoint. In some cases, to rebuild an address mapping after an asynchronous power loss, the memory system may access a last stored checkpoint to determine whether the checkpoint was stored as part of a sequential write mode. The memory system may generate logical addresses for data stored after the last checkpoint and before the asynchronous power loss using a starting logical address, as well as an ending logical address.

Techniques for sequential access operations

Methods, systems, and devices for improving write quality in memory systems are described. The memory system may receive, from a host system, a command to perform an operation. The memory system may determine an availability parameter that indicates processing resources of the memory system that are available to perform the operation based on receiving the command. In some cases, the memory system may transmit, to the host system, a message comprising the availability parameter, and the host system may delay transmission of one or more pending commands based on receiving the message comprising the availability parameter.

Write quality in memory systems

Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Dual address encoding for logical-to-physical mapping

Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

Dynamic status registers array

In some implementations, a memory device may receive a write command that includes data to be written to the memory device. The memory device may receive an indication that single-level cell data caching is deactivated for the data. The memory device may determine whether the data is associated with a first data type or a second data type. The memory device may selectively write the data to single-level cell cache memory or multi-level cell main memory based on a determination of whether the data is associated with the first data type or the second data type and a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.

Opportunistic storage of non-write-boosted data in write booster cache memory

Methods, systems, and devices for error detection event mechanism are described. The memory system may identify a fault condition and transmit, to a host system, a message indicating a first indication that the fault condition exists at the memory system. In some cases, the memory system may set, in a register of the memory system, a second indication indicating a type of the fault condition based on identifying the fault condition. The memory system may perform a recovery procedure based on the first indication and the second indication.

Error detection event mechanism

Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising a response information unit having a limited size with separate categories of information including changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information, wherein the information in the separate categories is based on the determined changes in the different L2P regions and the subregion information in each of the separate categories identifies specific locations of changed subregions with respect to one or more corresponding regions identified in the region information of a respective category of the response information unit.

Host logical-to-physical information refresh

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Low-power boot-up for memory systems

Methods, systems, and devices for signaling memory zone ranking information are described. A first system may determine ranking information for zones of a memory. The ranking information may be associated with a first type of maintenance operation. The first system may transmit the ranking information to a second system. The second system may use the ranking information to manage a second type of maintenance operation.

Signaling memory zone ranking information

Methods, systems, and devices for techniques for memory system rebuild are described. In some cases, a memory system may store an indication of whether data stored to one or more physical addresses is sequential using metadata associated with the one or more physical addresses. For metadata corresponding to a beginning physical address, the memory system may store an indication of a quantity of physical addresses subsequent to the beginning physical address with sequential corresponding logical addresses. Additionally or alternatively, the memory system may store an indication of a quantity of physical addresses preceding a last physical address with sequential corresponding logical addresses. During a rebuild operation, the memory system may read the stored indication and may rebuild an address mapping algorithmically using the stored indication.

Growing community of inventors

Boise, ID, United States of America

Giuseppe Cariello