Micron Technology Incorporated

Giuseppe Cariello

Jonathan Scott Parry

Fulvio Rori

Reshmi Basu

Deping He

Chiara Cerafogli

Luca Porzio

David Aaron Palmer

Scott Anthony Stoller

Jonathan W Oh

Harish Reddy Singidi

Preston Allen Thomson

Devin M Batutis

Roberto Izzi

Jung Sheng Hoei

Qing Liang

Ugo Russo

Mauro Luigi Sali

Marco Domenico Tiburzi

Stefano Falduti

Justin Bates

Kishore Kumar Muchherla

Stephen D Hanna

Christian M Gyllenskog

Antonino Pollio

Pitamber Shukla

Carmine Miccoli

Jameer Mulani

Nitul Gohain

Jeffrey Scott McNeil, Jr

Ryan Hrinya

Gaspare Giglio

Patrick Miesen

Methods, systems, and devices for improving write quality in memory systems are described. The memory system may receive, from a host system, a command to perform an operation. The memory system may determine an availability parameter that indicates processing resources of the memory system that are available to perform the operation based on receiving the command. In some cases, the memory system may transmit, to the host system, a message comprising the availability parameter, and the host system may delay transmission of one or more pending commands based on receiving the message comprising the availability parameter.

Write quality in memory systems

Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Dual address encoding for logical-to-physical mapping

Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

Dynamic status registers array

In some implementations, a memory device may receive a write command that includes data to be written to the memory device. The memory device may receive an indication that single-level cell data caching is deactivated for the data. The memory device may determine whether the data is associated with a first data type or a second data type. The memory device may selectively write the data to single-level cell cache memory or multi-level cell main memory based on a determination of whether the data is associated with the first data type or the second data type and a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.

Opportunistic storage of non-write-boosted data in write booster cache memory

Methods, systems, and devices for error detection event mechanism are described. The memory system may identify a fault condition and transmit, to a host system, a message indicating a first indication that the fault condition exists at the memory system. In some cases, the memory system may set, in a register of the memory system, a second indication indicating a type of the fault condition based on identifying the fault condition. The memory system may perform a recovery procedure based on the first indication and the second indication.

Error detection event mechanism

Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising a response information unit having a limited size with separate categories of information including changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information, wherein the information in the separate categories is based on the determined changes in the different L2P regions and the subregion information in each of the separate categories identifies specific locations of changed subregions with respect to one or more corresponding regions identified in the region information of a respective category of the response information unit.

Host logical-to-physical information refresh

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Low-power boot-up for memory systems

Methods, systems, and devices for signaling memory zone ranking information are described. A first system may determine ranking information for zones of a memory. The ranking information may be associated with a first type of maintenance operation. The first system may transmit the ranking information to a second system. The second system may use the ranking information to manage a second type of maintenance operation.

Signaling memory zone ranking information

Methods, systems, and devices for techniques for memory system rebuild are described. In some cases, a memory system may store an indication of whether data stored to one or more physical addresses is sequential using metadata associated with the one or more physical addresses. For metadata corresponding to a beginning physical address, the memory system may store an indication of a quantity of physical addresses subsequent to the beginning physical address with sequential corresponding logical addresses. Additionally or alternatively, the memory system may store an indication of a quantity of physical addresses preceding a last physical address with sequential corresponding logical addresses. During a rebuild operation, the memory system may read the stored indication and may rebuild an address mapping algorithmically using the stored indication.

Techniques for memory system rebuild

Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.

Dynamic memory address write policy translation based on performance needs

Methods, systems, and devices for configurable types of write operations are described. A memory device may receive a write command to write data in a zone of a memory system. The memory device may identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command. In some examples, the cursor may be associated with a type of a write operation based on a quantity of data associated with the cursor. As such, the memory device write, using a first type of the write operation or a second type of the write operation in accordance with the quantity of data, the data, and an indication of the type of the write operation used to write the data into the memory system.

Configurable types of write operations

Methods, systems, and devices for distributed power up for a memory system are described. The method may include a memory system receiving, from a host system, a command to initialize a set of memory devices included in a memory system. Upon receiving the command, the memory system may select a first memory device from the set of memory devices and read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device. The memory system may then read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of the set of memory devices.

Distributed power up for a memory system

Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.

Atomic write operations

Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

Techniques for suspend operations

The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.

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Boise, ID, United States of America

Giuseppe Cariello