Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Patent-treuhand-gesellschaft Fuer Elektrische Gluehlampen Mbh

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Dora S.p.a.

Giuseppe Cantone

Francesco Pulvirenti

Roberto Gariboldi

Angelo Genova

Roberto Cappelletti

Vincenzo Marano

Mario Tarantola

Giovanni Caggegi

Marco Giovanni Fontana

Marco Riva

Fabrizio Bognanni

Klaus Fischer

Aldo Vittorio Novelli

Vincenzo Palumbo

Alessandro Lasciandare

Barbara Antonelli

Antonello Castigliola

Roberto Aletti

Alessandro Nizza

A circuit includes a current path and a negative bootstrap circuitry coupled to the current path. The current path is coupled between a floating voltage and a reference ground, and includes a current generator coupled through a resistor to the floating voltage at a first node of the current generator. The current generator is controlled by a pulse signal. The negative bootstrap circuitry includes a pump capacitor coupled to a second node of the current generator and to the reference ground. The pump capacitor is configured to provide a negative voltage at the second node of the current generator based on the pulse signal.

Circuit to transfer a signal between different voltage domains and corresponding method to transfer a signal

A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

Driver circuit, corresponding device and method of operation

A circuit with galvanic isolation includes a series of n cascaded transformers including a first transformer and a last transformer in the series. A transmitter is coupled to the primary winding of the first transformer in the series of cascaded transformers, the transmitter being configured for supplying to the primary winding a transmission signal as a function of an input signal. A receiver is coupled to the secondary winding of the last transformer of the series of cascaded transformers and is configured for receiving at the secondary winding a reception signal transmitted over the series of cascaded transformers. A predistortion module is configured for applying to the transmission signal a predistortion including an (n&#x2212;1)-fold integration, where n is the number of cascaded transformers, of a transmission signal that would be supplied to the input of a sole transformer present in a single-transformer solution.

Method of transferring signals via transformers, corresponding circuit and device

A circuit provides a high-voltage low-drop diode-like conductive path between a DC voltage supply terminal and a bootstrap terminal in charging a supply capacitor for driving a power switch with the capacitor set between the bootstrap terminal and an output terminal alternatively switchable between a low voltage and a high voltage DC voltage. In an embodiment, the circuit includes first and second transistors such as LDMOS depletion transistors with the first transistor set in a cascode arrangement between the bootstrap terminal and the DC voltage supply terminal and the second transistor coupled with a sense comparator for comparing the voltage at the bootstrap terminal with the voltage at said DC voltage supply terminal. The first and second transistors have common control terminals coupled with the DC voltage supply terminal and common coupling terminals to the bootstrap terminal.

Driver circuit, corresponding integrated circuit and device

An electronic synchronous/asynchronous transceiver device for power line communication networks is integrated into a single chip and operates from a single supply voltage. The transceiver device includes: at least an internal register that is programmable through a synchronous serial interface; at least a line driver for a two-way network communication over power lines implemented by a single ended power amplifier with direct accessible input and output lines that is part of a tunable active filter for the transmission path; and at least a couple of linear regulators for powering with different voltage levels different kind of external controllers linked to the transceiver device.

Electronic synchronous/asynchronous transceiver device for power line communication networks

A data transceiving station of digital data frames includes a digital modem coupled to a transmission line, and a microprocessor receiving demodulated data from the modem according to a Packet Mode or a Bit Mode transmission through an interface circuit. The interface circuit switches between the Packet Mode and the Bit Mode transmission during transfer of a data frame to the microprocessor. The data transceiving station combines the superior speed of a Packet Mode transfer with the unlimited compatibility of a Bit Mode transfer.

Multichannel transceiver of digital signals over power lines

Functions for simulating, burning and controlling integrated fuses of a device are provided by a dedicated circuit which, instead of differing from other circuits, is integrated by sharing part of the registers with the circuit that normally exists to scan test the integrity of the state of the device. The architecture is simplified and only requires an additional pin as compared to a common scan test circuit.

System of management of the trimming of integrated fuses within a scan test architecture

A method for controlling the level of a signal produced by a transceiver of digital data coupled to a power distribution line during a transmission phase is provided. The level of the signal output by the transceiver is regulated by comparing the current level of the output signal with a predetermined minimum threshold and a predetermined maximum threshold, reducing the current level when the maximum threshold is exceeded by reducing the gain, and switching to a voltage mode control of the output signal when the current level of the output signal becomes lower than the minimum threshold.

Control of the level of the signal produced by a transceiver coupled to a power distribution line

An integrated device for a switching system is disclosed. The device includes control circuitry for generating at least one switching control signal, reference circuitry for generating at least one reference quantity, a using circuit for using the reference quantity, a circuit for storing the reference quantity, and a switch which, in a first operative condition, connects the reference circuit to the using circuit and to the storage circuit in order to apply the reference quantity thereto. In a second operative condition, the switch disconnects the reference circuit from the using circuit and connects the storage circuit to the using circuit in order to apply the stored reference quantity thereto. Finally, the device includes filtering circuitry for keeping the switch in the second operative condition for a filtering period in accordance with the switching of the control signal.

Integrated device for switching systems with filtered reference

A circuit is described with which an operation circuit for a discharge lamp can be switched between operation states with different lamp currents by hort interruptions of the power supply. Long interruptions than a certain time threshold result in basic state operation.

Operation circuit in particular for discharge lamps using discrete time

A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance. The LDMOS transistor is controlled via a bootstrap capacitor charged by a diode at the supply voltage of the circuit, and by an inverter driven by a logic control circuit as a function of a Low Gate Drive Signal and of a second logic signal which is active during a phase wherein the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit uses a first zener diode to charge the bootstrap capacitor and the source of the transistor is connected to the supply node through a second zener diode.

Turn-off circuit for an LDMOS in presence of a reverse current

A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap capacitor charged by a diode connected to the supply node of the circuit, and by an inverter driven by a logic control circuit as a function of a first Low Gate Drive Signal and of a second logic signal. The second logic signal is active during a phase where the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit further includes a second inverter functionally referred to the charging node of the bootstrap capacitor and to the voltage of the output node of the inverter. The second inverter has an input coupled to the second logic signal and an output coupled to the gate node of the LDMOS transistor for preventing accidental undue switch-on of the LDMOS transistor.

Protection circuit for controlling the gate voltage of a hv LDMOS

A circuit for charging a capacitance using an LDMOS integrated transistor controlled in a manner to emulate a high voltage charging diode of the capacitance. The circuit avoids the switch-on of parasitic bipolar transistors of the LDMOS structure during transient states. The circuit includes a number of junctions directly biased between a source node and a body node of the LDMOS transistor, a current generator referred to a ground of the circuit, at least one switch between the source and a first junction of a chain of directly biased junctions, and a limiting resistor connected between the body and the current generator referred to ground. The switch is open during a charging phase of the capacitance and is closed when the charging voltage of the capacitance exceeds a preestablished threshold responsive to a control signal. The switch is controlled by a logic signal active during the phase in which the supply voltage of the integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit, for charging the body with a current whose maximum value is limited to a preestablished value.

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Siracusa, Italy

Giuseppe Cantone