Stmicroelectronics S.r.l.

Giuseppe Arena

Giuseppe Ferla

Angelo Magri′

Salvatore Leonardi

Salvatore Coffa

Angelo Magri'

Marco Camalleri

Domenico Repici

Orazio Battiato

Fabrizio Marco Di Paola

Angelo Magri

Cateno Marco Camalleri

Giuseppe D'Arrigo

Roberto Modica

Domenico Murabito

Giuseppe Morale

Caterina Donato

Corrado Spinella

Letterio Fiore

A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.

Method for manufacturing a high integration density power MOS device

According to an embodiment of a method for manufacturing a MISFET device, in a semiconductor wafer, a semiconductor layer is formed, having a first type of conductivity and a first level of doping. A first body region and a second body region, having a second type of conductivity, opposite to the first type of conductivity, and an enriched region, extending between the first and second body regions are formed in the semiconductor layer. The enriched region has the first type of conductivity and a second level of doping, higher than the first level of doping. Moreover, a gate electrode is formed over the enriched region and over part of the first and second body regions, and a dielectric gate structure is formed between the gate electrode and the semiconductor layer, the dielectric gate structure having a larger thickness on the enriched region and a smaller thickness on the first and second body regions. To form the enriched region, a first conductive layer is made on the semiconductor layer, an enrichment opening is formed in the first conductive layer, and a dopant species is introduced into the semiconductor layer through the enrichment opening. Furthermore, the formation of the dielectric gate structure envisages filling the enrichment opening with dielectric material, prior to forming the first body region and the second body region.

Manufacturing process of a vertical-conduction MISFET device with gate dielectric structure having differentiated thickness and vertical-conduction MISFET device thus manufacture

A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.

Method of manufacturing a semiconductor power device

A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.

Dielectric insulation structure for integrating electronic semiconductor devices and relevant manufacturing process

A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

Method for manufacturing a SOI wafer

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Catania, Italy

Giuseppe Arena