Other

Skhynix Inc.

Hynix Semiconductor Inc.

Stmicroelectronics S.r.l.

Giulio Martinozzi

Stefano Zanardi

Osama Khouri

Lorenzo Di Lalla

Federica Arosio

Min Sang Park

Mauro Pagliato

Sang Jo Lee

Francesco Pessina

Disclosed herein is a method for managing of NOP instructions in a microcontroller, the method comprising duplicating all jump instructions causing a NOP instruction to form a new instruction set; inserting an internal NOP instruction into each of the jump instructions; when a jump instruction is executed, executing a subsequent instruction of the new instruction set; and executing the internal NOP instruction when an execution of the subsequent instruction is skipped.

Method performed by a microcontroller for managing a NOP instruction and corresponding microcontroller

A method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment.

Method and controller for programming non-volatile memory

A device includes a nonvolatile memory array, a Static Random Access Memory (SRAM) array including a plurality of bit lines, including first and second bit lines paired with each other, and a pad. A first circuit is coupled between the nonvolatile memory array and the first and second bit lines, and interfaces with the SRAM array. A second circuit is coupled between the pad and the first and second bit lines, and interfaces with the SRAM array. A control circuit performs a first operation to access the nonvolatile memory array via the SRAM array and the first and second circuits and performs a second operation by producing an electrical path connecting from the pad to the nonvolatile memory array through at least one of the first and second bit lines of the SRAM array without intervening at least one of the first and second circuits.

DMA architecture for NAND-type flash memory

A page buffer for an electrically programmable memory includes a plurality of storage units, each comprising a first latch and a second latch. Input switching means loads into the latch the data bit to be written and to be temporarily stored. The input switching means has an input terminal connected to the respective data line for receiving a set voltage provided therethrough. The input switching means provides the set voltage to the first or second input/output terminals of the latch depending on the data bit to be written. An output switch device transfers onto the respective data line the read data bit temporarily stored into the latch and has a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.

Page buffer circuit and method for a programmable memory device

A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.

Method of transferring data in an electrically programmable memory

A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.

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Agrate Brianza, Italy

Giulio Martinozzi