Skhynix Inc.

Giulio Maria Iadicicco

Yong Tae Kim

Marco Passerini

Moon Soo Sung

Dario Melchionni

Miriam Sangalli

A switching architecture provides input voltage signals from input voltage lines to a plurality of global word lines connected to word lines of a memory array in a memory device. The switching architecture includes a first switching block receiving a first set of positive voltages used to bias unselected word lines and being connected to a first output line providing a first output bias voltage, and a second switching block receiving a second set of positive voltages and a third set of negative voltages used to bias selected word lines and being connected to a second output line providing a second output bias voltage. A plurality of final switches are input connected to the first and second output lines and are output connected to a respective global word line.

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Agrate Brianza, Italy

Giulio Maria Iadicicco