Micron Technology Incorporated

Texas Instruments Corporation

Giulio-Giuseppe Marotta

Marco-Domenico Tiburzi

Agostino Macerola

Vishal Sarin

Jung Sheng Hoei

Elio D'Ambrosio

Frankie F Roohparvar

Michael C Smayling

Giovanni Santin

Frankie F Roohpavar

Satoru Fukawa

Misako A Matsuoka

Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Apparatuses, circuits, and methods for biasing signal lines

Apparatus, devices, systems, and methods are described that include variable state material data storage. Example devices include current compliance circuits that are configured to dynamically adjust a current passing through a variable resistance material during a memory operation. Some configurations utilize components within an array of memory cells to form a current compliance circuit. Additional apparatus, systems, and methods are described.

Apparatuses including current compliance circuits and methods

Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.

Apparatuses and methods for providing set and reset voltages at the same time

The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.

Sensing memory cells

Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

Memory cell sensing using negative voltage

A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2&#x2212;1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2&#x2212;1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

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Contigliano, Italy

Giulio-Giuseppe Marotta