Micron Technology Incorporated

Texas Instruments Corporation

Other

Intel Corporation

Round Rock Research, LLC

Giulio Giuseppe Marotta

Tommaso Vali

Giovanni Santin

Michael C Smayling

Girolamo Gallo

Marco Domenico Tiburzi

Luca De Santis

Agostino Macerola

Marco-Domenico Tiburzi

Alessandro Torsi

Pietro Piersimoni

Giuliano Imondi

Giuseppe Savarese

Giulio Porrovecchio

Frankie F Roohparvar

Carlo Musilli

Stefano Perugini

Cristina Lattaro

Violante Moschiano

Giovanni Naso

Sebastiano D'Arrigo

Tito Gelsomini

Eros Pasero

Satoru Fukawa

Misako A Matsuoka

Pranav Kalavade

Michele Incarnati

Luigi Pilolli

Umberto Siciliani

Georges Falessi

Ercole Di Iorio

Mousumi Bhat

Iano D'Arrigo

Luciano Talamonti

Giovani Santin

Violante Moshciano

Ercole Di Lorio

Virtual ground sensing circuits, control circuit, electrical systems, computing devices, and related methods are disclosed. A control circuit includes a virtual ground sensing circuit configured to provide a virtual ground to a conductive line. The virtual ground sensing circuit is further configured to selectively operably couple the conductive line to a sense node of a sense circuit, wherein the sense node having a sense node capacitance less than a capacitance of the conductive line. Further, virtual ground sensing circuit is configured to compare a sense node voltage to a reference voltage.

Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory

Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.

Read and program operations in a memory device

Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Memory devices for pattern matching

A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.

Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.

Methods and apparatus for pattern matching are disclosed. In at least one embodiment, pattern checking is accomplished by reading a page of memory, and comparing the read page with the pattern to be searched in a logic operation. In at least one other embodiment, a pattern to be searched is stored in registers where each bit of the pattern is stored using two register entries and each bit of the array data is stored using two cells of the array.

Methods and apparatus for pattern matching

Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.

Erasing physical memory blocks of non-volatile memory

Dynamic SLC/MLC blocks allocations for non-volatile memory

Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.

Voltage switching in a memory device

Growing community of inventors

Contigliano, Italy

Giulio Giuseppe Marotta